High-availability computer system with a predefinable configuration of the modules

Claim 1

A high-availability-computer system having a plurality of VLSI modules, said system operative during an initialization phase to initialize said modules and during a non-initialization phase subsequent to said initialization phase to transfer information between the modules initialized during said initialization phase comprising: a multi-bit wide module bus having a plurality of signal lines beginning with a least-significant-bit signal line of said module bus and ending with a most-significant-bit signal line of said module bus; a processor module connected to said module bus; said processor module having bidirectional address lines and data lines connected to said module bus; a memory array, having two memory-control-unit modules, each connected to said module bus for exchanging address and data with said processor module over said bidirectional address and data lines; a system bus; a first bus extension-unit module connecting said processor module to said system bus; a second and third bus extension-unit module connecting each of said memory control unit modules to said system bus; a power-supply module having a system support module which generates an initialization signal upon switching on; said system support module having an initialization signal line connected to each of said VLSI modules over which said initialization signal is transmitted to begin said initialization phase of said computer system; said processor module, said memory-control-unit modules, and said bus extension-unit modules each being provided with an initialization identification pin; said processor module, said memory-control-unit modules, and said bus extension-unit modules each having its respective initialization identification pin connected to a respective different signal line of said module bus; identification command generating means in said processor, connected to said module bus, for generating successive identification command information, which identification command information firstly activates a module to receive information and secondly assigns an identification code to the activated module; each of said identification commands containing a first data record and a second data record, said first data record being comprised of a first data field of bits equal to the number of signal lines in said multi-bit module bus, with only one logical one in said first data field, the position of said logical one advancing consecutively from said least significant bit position to said most significant bit position for each successive identification command generated by said identification command generating means in said processor; and, said second data record being comprised of a second data field of bits which include an identification code uniquely identifying the one of said modules activated over its initialization identification pin by said first record to receive said second record and hence its identification code.