Patent US4975699A successfully refreshed from Google Patents.
US4975699A
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Error reduction method and apparatus for a direct digital synthesizer
Assignee: Raytheon Co
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Filing: 1989-12-01
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Granted: 1990-12-04
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Expires: 2009-12-01
Abstract
Abstract A circuit for generating an analog sine voltage from a digital phase input (11) employing a memory (13) storing sine and cosine values and a correction value for each phase and first and second digital-to-analog converters (DACs) (19,21). For each digital phase input (N), selected sine and cosine values are combined and the result is read out to the first DAC (19), which generates an analog sine approximation voltage. A corresponding correction value is simultaneouosly read out to the second DAC (21), whose output is scaled by an attenuator (23) to provide a correction voltage for correcting the deviation in the output voltage of the first DAC (19) from the ideal sine voltage value.
Inventors
- 👤 Gary D. Frey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:57
CPC Classifications
G; G06; G06J; G06J1/00; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/035; G06F1/0356; G06F2101/00; G06F2101/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
180 words
Circuitry for converting a digital input comprising an N bit word including A bits and B bits where A and B are integers and A+B=N into a desired sine voltage, said circuitry comprising: a memory means addressed by said A bits, said memory means storing binary sine values, binary cosine values and binary correction values for outputting a selected sine A value, cosine A value and correction value in response to a selected address of A bits; means for forming a binary output comprising the expression sin (A)+B cos (A) from said selected sin (A) and cos (A) values; a first digital-to-analog converting means for converting said binary output to an analog sine approximation voltage exhibiting a deviation from the desired sine voltage; and means receiving a selected one of said correction values for generating a compensation voltage for compensating for said deviation from said desired sine voltage, said means including a second digital-to-analog converting means for converting said correction value to an analog correction voltage; and attenuation means for attenuating said analog correction voltage for generating said compensation voltage.
Claim 2
Dependent Claim
180 words
Circuitry for converting a digital input comprising an N bit word including A bits and B bits where A and B are integers and A+B=N into a desired sine voltage, said circuitry comprising: a memory means addressed by said A bits, said memory means storing binary sine values, binary cosine values and binary correction values for outputting a selected sine A value, cosine A value and correction value in response to a selected address of A bits; means for forming a binary output comprising the expression sin (A)+B cos (A) from said selected sin (A) and cos (A) values; a first digital-to-analog converting means for converting said binary output to an analog sine approximation voltage exhibiting a deviation from the desired sine voltage; and means receiving a selected one of said correction values for generating a compensation voltage for compensating for said deviation from said desired sine voltage, said means including a second digital-to-analog converting means for converting said correction value to an analog correction voltage; and attenuation means for attenuating said analog correction voltage for generating said compensation voltage.
Claim 3
Dependent Claim
18 words
The circuitry of claim 1 further including means for adding said compensation voltage to said sine approximation voltage.
Claim 4
Dependent Claim
49 words
The circuitry of claim 2 wherein said first and second digital-to-analog converting means have a selected bit width and wherein said attenuation means attenuates said analog correction voltage by a factor of 1/2 a , wherein the exponent "a" is the bit width of said second digital-to-analog converting means.
Claim 5
Dependent Claim
25 words
The circuitry of claim 3 wherein the bit width of said first analog-to-digital converting means equals the bit width of said second analog-to-digital converting means.
Claim 6
Dependent Claim
53 words
The circuitry of claim 4 wherein said means for forming comprises: a multiplier receiving said B bits and the selected cos (A) values and having an output; and an adder receiving said output of said multiplier and said selected sin (A) values and having an output connected to said first digital-to-analog converting means.
Claim 7
Independent Claim
85 words
A method of compensating for errors in a circuit wherein digital approximations of trigonometric values are stored in a memory and used to generate a sine approximation value for supply to a digital-to-analog converter (DAC) which generates a sine approximation voltage, comprising the steps of: measuring the deviation of said sine approximation voltage from the desired sine voltage; deriving a digital correction value for compensating for said deviation; storing said digital correction value; and employing the stored digital correction value to compensate for said deviation.
Claim 8
Independent Claim
85 words
A method of compensating for errors in a circuit wherein digital approximations of trigonometric values are stored in a memory and used to generate a sine approximation value for supply to a digital-to-analog converter (DAC) which generates a sine approximation voltage, comprising the steps of: measuring the deviation of said sine approximation voltage from the desired sine voltage; deriving a digital correction value for compensating for said deviation; storing said digital correction value; and employing the stored digital correction value to compensate for said deviation.
Claim 9
Dependent Claim
37 words
The method of claim 6 wherein said step of employing comprises the steps of: converting said digital correction value to an analog voltage; attenuating said analog voltage; and adding said analog voltage to said sine approximation voltage.
References Cited (Backward Citations)
US4476536A
Cited
US4809205A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-12-03 | 1994-06-04 | 1994-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-03 | 1998-06-04 | 1998-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-03 | 2002-06-04 | 2002-12-04 | $7700.00 | Window Closed / Lapsed |