US4974188A — Address sequence generation by means of reverse c…

Claim 1

Independent Claim 193 words

An apparatus for generating a repetitive bit reverse address sequence starting at a selected binary starting address and using a binary incrementing code to designate sequence size, said apparatus comprising: a current address register loaded with an instruction containing a current binary address and information designating said binary incrementing code, wherein said current binary address is initially said binary starting address; a reverse carry addition means coupled to said current address register for reverse carry addition of said incrementing code with said current binary address to generate a next binary address in said bit reverse address sequence, wherein said next binary address is written into said current address register as said current address, wherein said binary incrementing code is an n-bit binary word selected from one of: ______________________________________ Sequence size Binary incrementing code ______________________________________ 2 0 . . . 01 4 0 . . . 010 8 0 . . . 0100 16 0 . . . 01000 32 0 . . . 010000 ______________________________________ wherein said incrementing code is selected to program the bit reverse address sequence size and therefore the number of address locations mapped into a particular closed memory space.

Claim 2

Independent Claim 193 words

An apparatus for generating a repetitive bit reverse address sequence starting at a selected binary starting address and using a binary incrementing code to designate sequence size, said apparatus comprising: a current address register loaded with an instruction containing a current binary address and information designating said binary incrementing code, wherein said current binary address is initially said binary starting address; a reverse carry addition means coupled to said current address register for reverse carry addition of said incrementing code with said current binary address to generate a next binary address in said bit reverse address sequence, wherein said next binary address is written into said current address register as said current address, wherein said binary incrementing code is an n-bit binary word selected from one of: ______________________________________ Sequence size Binary incrementing code ______________________________________ 2 0 . . . 01 4 0 . . . 010 8 0 . . . 0100 16 0 . . . 01000 32 0 . . . 010000 ______________________________________ wherein said incrementing code is selected to program the bit reverse address sequence size and therefore the number of address locations mapped into a particular closed memory space.

Claim 3

Dependent Claim 63 words

The apparatus of claim 1, wherein said binary starting address is an n-bit binary word having the following format: ______________________________________ Sequence size Binary Starting Address ______________________________________ 2 X . . . XXX0 4 X . . . XX00 8 X . . . X000 16 X . . . X0000 64 X . . . X00000 ______________________________________ where X is any binary bit.

Claim 4

Dependent Claim 82 words

The apparatus of claim 2, wherein said reverse carry adder means further comprises: a plurality of full-adder circuits cascaded to form a ripple carry array with the output carry of each particular full-adder circuit connected to the carry input of the full-adder circuit to right of said particular full-adder circuit, wherein carry information ripples from most significant bit addition to the leasdt significant bit addition and said full-adder circuits produces as an output a next binary address in said bit feverse sequence.

Claim 5

Dependent Claim 160 words

The apparatus of claim 2, wherein said reverse carry adder means further comprises: a look-ahead adder circuit having inputs (X n . . . X o ) and (Y n . . . Y o ) producing as an output a next binary address in said bit reverse sequence where X n and Y n are most significant bits; a means for inputting the current binary address (A n . . . A o ) in reversed order so that the most significant bit (A n ) is connected to the least significant input bit (X ok ) of said look-ahead adder circuit; and, a means for inputting the binary incrementing code (B n . . . B o ) in reversed order so that the most significant input bit (Y o ) of said look-ahead adder circuit, so taht the carry bit propagation in the look-ahead adder circuit propagates from most significant bit position to least significant bit position.

Claim 6

Dependent Claim 181 words

The apparatus of claim 2, wherein said reverse carry adder means further comprises: a calculation means, receiving said current address (A n . . . A o ) and said binary incrementing code (B n . . . B o ) as inputs, for calculating generation functions (G i ) and propagation functions (P i ) for i=0 to n, where G.sub.i =A.sub.i.B.sub.i P.sub.i =A.sub.i ⊕B.sub.i ; a reverse carry means, coupled to said calculation means to receive said generation functions (G i ) and propagation functions (P i ) as inputs, for calculating reverse carry expressions (C i ) for i=1 to n where, C.sub.n =0 Ci.sub.-1 =Gi.sub.-1 +C.sub.i.Pi.sub.-1 ; and, a summation means coupled to said calculation means and said reverse carry means to receive propagation functions (P i ) and reverse carry expressions (C i ) for calculating and providing as output summation expressions (S i ) where S n =P n-1 +C in and S i-1 =P i-1 +C i for i=n to 0, wherein S i is a next binary address in said bit reverse sequence.

Claim 7

Independent Claim 206 words

An apparatus for generating a repetitive address sequence starting at a selected binary starting address and using a binary incrementing code to designate the number of address locations mapped into a closed memory space, said apparatus comprising: a current address register loaded with an instruction containing a current binary address and information designating said binary incrementing code, wherein said current binary address is initially said binary starting address; and, a reverse carry addition means coupled to said current address register for reverse carry addition of said incrementing code with said current binary address to generate a next binary address, wherein said next binary address is written into said current address register as said current address, wherein said binary incrementing code is an n-bit binary word selected from one of: ______________________________________ Sequence Size Binary Starting Address ______________________________________ 2 0 . . . 01 4 0 . . . 01X 8 0 . . . 01XX 16 0 . . . 01XXX 32 0 . . . 01XXXX 64 0 . . . 01XXXXX ______________________________________ wherein X is any binary bit and wherein said incrementing code is selected to program the address sequence size and therefore the number of address locations mapped into a particular closed memory space.

Claim 8

Independent Claim 206 words

An apparatus for generating a repetitive address sequence starting at a selected binary starting address and using a binary incrementing code to designate the number of address locations mapped into a closed memory space, said apparatus comprising: a current address register loaded with an instruction containing a current binary address and information designating said binary incrementing code, wherein said current binary address is initially said binary starting address; and, a reverse carry addition means coupled to said current address register for reverse carry addition of said incrementing code with said current binary address to generate a next binary address, wherein said next binary address is written into said current address register as said current address, wherein said binary incrementing code is an n-bit binary word selected from one of: ______________________________________ Sequence Size Binary Starting Address ______________________________________ 2 0 . . . 01 4 0 . . . 01X 8 0 . . . 01XX 16 0 . . . 01XXX 32 0 . . . 01XXXX 64 0 . . . 01XXXXX ______________________________________ wherein X is any binary bit and wherein said incrementing code is selected to program the address sequence size and therefore the number of address locations mapped into a particular closed memory space.

Claim 9

Dependent Claim 15 words

The apparatus of claim 6, wherein said binary starting address is any n-bit binary word.

Claim 10

Dependent Claim 72 words

The apparatus of claim 7, wherein said reverse carry adder means further comprises: a plurality of full-adder circuits cascaded to form a ripple carry array with the output carry of each full-adder circuit connected to the carry input of the full-adder circuit to its right, wherein carry information ripples from most significant bit addition to the least significant bit addition and said full-adder circuits produces as an output a next binary address.

Claim 11

Dependent Claim 172 words

The apparatus of claim 7, wherein said reverse carry adder means further comprises: a look-ahead adder circuit having inputs (X n . . . X o ) and (Y n . . . Y o ) producing as an output a next binary address (S h . . . S o ) where X n and Y n are most significant bits; a means for inputting current binary address (A n . . . A o ) in reversed order so that the most significant bit (A n ) is connected to the least significant input bit (X o ) of said look-ahead adder circuit; and, a means for inputting the binary incrementing code (B n . . . B o ) in reversed order so that the most significant bit (B n ) is connected to the least significant input bit (Y o ) of said look-ahead adder circuit, so that the carry bit propagation in the look-ahead adder circuit propagates from most significant bit position to least significant bit position.

Claim 12

Dependent Claim 177 words

The apparatus of claim 16, wherein said reverse carry adder means further comprises: a calculation means, receiving said current binary address (A n . . . A o ) and said binary incrementing code (B n . . . B o ) as inputs, for calculating generation functions (G i ) and propagation functions (P i ) for i=0 to n, where G.sub.i =A.sub.i.B.sub.i P.sub.i =A.sub.i ⊕B.sub.i ; a reverse carry means, coupled to said calculation means to receive said generation functions (G i ) and propagation functions (P i ) as inputs, for calculating reverse carry expressions (C i ) for i=1 to n where, C.sub.n =0 Ci.sub.-1 =Gi.sub.-1 +C.sub.i.Pi.sub.-1 ; and, a summation means coupled to said calculation means and said reverse carry means to receive propagation functions (P i ) and reverse carry expressions (C i ) for calculating and providing as output summation expressions (S i ) where S n =P n-1 +C n and S i-1 =P i-1 +C i for i=n to 0, wherein S i is a next binary address.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1993-11-26	1994-05-28	1994-11-27	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1997-11-26	1998-05-28	1998-11-27	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2001-11-26	2002-05-28	2002-11-27	$7700.00	Window Closed / Lapsed

Address sequence generation by means of reverse carry addition

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