Neural network with memory cycling

Claim 2

An information processing method to calculate output values for a group of neurons, each of the neurons having a plurality of inputs, the method comprising: transmitting input values for the neurons to a memory unit of a processing section, the memory unit including at least first and second areas; calculating a plurality of series of neuron output values over plurality of cycles, each cycle including at least first and second periods, and including (i) during the first period of each cycle, calculating a first series of neuron output values from neuron input values stored in the first memory area, and (ii) during the second period of each cycle, calculating a second series of neuron output values from neuron input values stored in the second memory area; and the transmitting step including the steps of (i) storing in the first memory area of the memory unit neuron input values that are transmitted to the memory unit during the period immediately preceding the first period of each cycle and that are used during said first period to calculate said first series of neuron output values, and (ii) storing in the second memory area of the memory unit, neuron input values that are transmitted to the memory unit during the first period of each cycle and that are used during the second period of the cycle to calculate said second series of neuron output values.

Claim 3

A method according to claim 1, wherein: the memory unit of the processing section further includes a third area; each of said cycles includes a third period; the step of calculating the plurality of series of neuron output values further includes the step of (iii) during the third period of each cycle, calculating a third series of neuron output values from neuron input values stored in the third memory area; the transmitting step further includes the step of (iii) storing in the third memory area, neuron input values transmitted to the memory unit during the second period of each cycle and that are used during the third period of the cycle to calculate said third series of neuron output values.

Claim 4

A method according to claim 2, wherein: each cycle consists of three periods; and the period immediately preceding the first period of each cycle is the third period of the immediately preceding cycle.

Claim 5

A method according to claim 1 wherein: all of the neuron input values transmitted to the memory unit during the period immediately preceding the first period of each cycle, are stored in the first memory area; and all of the neuron input values transmitted to the memory unit during the first period of each cycle are stored in the second memory area.

Claim 6

A method according to claim 3, wherein: all of the neuron input values transmitted to the memory unit during the third period of each cycle are stored in the first memory area; all of the neuron input values transmitted to the memory unit during the first period of each cycle are stored in the second memory area; and all of the neuron input values transmitted to the memory unit during the second period of each cycle are stored in the third memory area.

Claim 7

A method according to claim 2, wherein the processing section further includes a multiply accumulator unit to calculate the neuron output values, a first data line to transmit neuron input values from the memory unit to the multiply accumulator unit, a second data line to transmit neuron input values to the memory unit, a first switching unit to control the transmission of neuron input values between the first memory area and the first and second data lines, a second switching unit to control the transmission of neuron input values between the second memory area and the first and second data lines, and a third switching unit to control the transmission of neuron input values between the third memory area and the first and second data lines, and wherein: the calculating step includes in the first period of each cycle, using the first switching unit to connect the first memory area to the first data line to transmit neuron input values from the first memory area to the multiply accumulator unit, in the second period of each cycle, using the second switching unit to connect the second memory area to the first data line to transmit neuron input values from the second memory area to the multiply accumulator unit, and in the third period of each cycle, using the third switching unit to connect the third memory area to the first data line to transmit neuron input values from the third memory area to the multiply accumulator unit; and the transmitting step includes the steps of in the first period of each cycle, using the second switching unit to connect the second memory area to the second data line to transmit neuron input values to the second memory area for use in the second period of the cycle, in the second period of each cycle, using the third switching unit to connect the third memory area to the second data lien to transmit neuron input values to the third memory area for use in the third period of the cycle, and in the third period of each cycle, using the first switching unit to connect the first memory area to the second data line to transmit neuron input values to the first memory area for use in the first period of the next cycle.

Claim 8

A method according to claim 1, wherein the processing section further includes multiply accumulator means to calculate the neuron output values, a first data line to transmit neuron input values from the memory unit to the multiply accumulator means, a second data line to transmit neuron input values to the memory unit, a first switching unit to control the transmission of neuron input values between the first memory area and the first and second data lines, and a second switching unit to control the transmission of neuron input values between the second memory area and the first and second data lines, and wherein: the calculating step includes in the first period of each cycle, using the first switching unit to connect the first memory area to the first data line to transmit neuron input values from the first memory area to the multiply accumulator means, and in the second period of each cycle, using the second switching unit to connect the second memory area to the second data line to transmit neuron input values from the second memory area to the multiply accumulator means; and the transmitting step includes the step of, in the first period of each cycle, using the second switching unit to connect the second memory area to the second data line to transmit neuron input values to the second memory area for use in the second period of the cycle.

Claim 9

An information processing system, comprising: at least one processing section to calculate output values for a plurality of neurons, each of the neurons having a plurality of inputs; input means to broadcast a plurality of neuron input values to the processing section; the processing section including (i) a memory unit including at least first and second memory areas to hold the neuron input values, (ii) calculating means to calculate a plurality of series of neuron output values over a plurality of cycles, each cycle including at least first and second periods, (iii) neuron input value transmission means to transmit neuron input values between the input means and the memory unit and between the memory unit and the calculating means, and adapted (a) to transmit neuron input values from the first memory area to the calculating means during the first period of each cycle to calculate a first series of neuron output values, and to transmit neuron input values from the second memory area to the calculating means during the second period of each cycle to calculate a second series of neuron output values, and (b) to transmit input values from the input means to the second area of the memory during the first period of each cycle, and to transmit input values to the first area of the memory unit during a period immediately preceding the first period of each cycle.

Claim 10

An information processing system, comprising: at least one processing section to calculate output values for a plurality of neurons, each of the neurons having a plurality of inputs; input means to broadcast a plurality of neuron input values to the processing section; the processing section including (i) a memory unit including at least first and second memory areas to hold the neuron input values, (ii) calculating means to calculate a plurality of series of neuron output values over a plurality of cycles, each cycle including at least first and second periods, (iii) neuron input value transmission means to transmit neuron input values between the input means and the memory unit and between the memory unit and the calculating means, and adapted (a) to transmit neuron input values from the first memory area to the calculating means during the first period of each cycle to calculate a first series of neuron output values, and to transmit neuron input values from the second memory area to the calculating means during the second period of each cycle to calculate a second series of neuron output values, and (b) to transmit input values from the input means to the second area of the memory during the first period of each cycle, and to transmit input values to the first area of the memory unit during a period immediately preceding the first period of each cycle.

Claim 11

An information processing system according to claim 8, wherein: the memory unit of the processing section includes a third area; each of said cycles includes a third period; and the transmission means is further adapted to transmit neuron input values from the third memory area to the calculating means during the third period of each cycle to calculate a third series of neuron output values, and to transmit neuron input values to the third area of the memory unit during the second period of each cycle.

Claim 12

An information processing system according to claim 8, wherein: the neuron input value transmission means includes (i) a first data line to transmit the neuron input values from the memory unit to the calculating means, (ii) a second data line to transmit the neuron input values to the memory unit, (iii) a first switching unit having a first state to connect the first memory area to the first data line to transmit neuron input values from the first memory area to the calculating means, and a second state connecting the first memory area to the second data line to transmit neuron input values to the second memory area, and (iv) a second switching unit having a first state to connect the second memory area to the first data line to transmit neuron input values from the second memory area to the calculating means and a second state connecting the second memory area to the second data line to transmit neuron input values to the second memory area; in the first period of each cycle, the first switching unit is in the first state thereof, and the second switching unit is in the second state thereof; and in the second period of each cycle, the second switching unit is in the first state thereof.

Claim 13

A system according to claim 10, further including control means connected to the first and second switching units to control the states thereof.

Claim 14

A system according to claim 11, wherein the control means is adapted to place the first switching unit into the first state thereof and to place the second switching unit in the second state thereof at the beginning of the first period of each cycle; and to place the second switching unit in the first state thereof at the start of the second period of each cycle.

Claim 15

An information processing system according to claim 9, wherein: the transmission means includes (i) a first data line to transmit the neuron input value from the memory unit to the calculating means, (ii) a second data line to transmit the neuron input values to the memory unit, (iii) a first switching unit having first state connecting the first memory area to the first data line to transmit neuron input values from the first memory area to the calculating means, and a second state connecting the first memory area to the second data line to transmit neuron input values to the first memory area; (iv) a second switching unit having a first state connecting the second memory area to the first data line to transmit neuron input values from the second memory area to the calculating means, and a second state connecting the second memory area to the second data line to transmit the neuron input values to the second memory area; and (v) a third switching unit having a first state connecting the third memory area to the first data line to transmit neuron input values from the third memory area to the calculating means, and a second state connecting the third memory area to the second data line to transmit neuron input values to the third memory area; in the first period of each cycle, the first switching unit is in the first state thereof and the second switching unit is in the second state thereof; in the second period of each cycle, the second switching unit is in the first state thereof and the third switching unit is in the second state thereof; and in the third period of each cycle, the third switching unit is in the first state thereof.

Claim 16

An information processing system according to claim 13, wherein, in the third period of each cycle, the first switching unit is the second state thereof.

Claim 17

An information processing system according to claim 13, further including control means connected to the first, second and third switching units to control the states thereof.

Claim 18

An information processing method to calculate output values for a multitude of neurons, each of the neurons having a plurality of inputs, the method comprising: broadcasting input values for the neurons to a plurality of processing sections; using each of the processing sections to calculate output values for a group of associated neurons, including (i) holding in each processing section, input values for the associated group of neurons, (ii) during a first period, using each processing section (a) to calculate a first series of neuron output values for the associated group of neurons, and (b) to broadcast said first series of neuron output values to the other processing sections, and (iii) during a second period, using each processing section (a) to calculate a second series of neuron output values for the associated group of neurons, and (b) to broadcast said second series of neuron output values to the other processing sections.

Claim 19

An information processing method to calculate output values for a multitude of neurons, each of the neurons having a plurality of inputs, the method comprising: broadcasting input values for the neurons to a plurality of processing sections; using each of the processing sections to calculate output values for a group of associated neurons, including (i) holding in each processing section, input values for the associated group of neurons, (ii) during a first period, using each processing section (a) to calculate a first series of neuron output values for the associated group of neurons, and (b) to broadcast said first series of neuron output values to the other processing sections, and (iii) during a second period, using each processing section (a) to calculate a second series of neuron output values for the associated group of neurons, and (b) to broadcast said second series of neuron output values to the other processing sections.

Claim 20

A method according to claim 16, wherein each neuron output value is calculated by only one of the processing sections.

Claim 21

A method according to claim 16, wherein: each processing section includes first and second memory areas; the holding step includes the step of (i) holding in the first memory area of each processing section input values used to calculate the first series of neuron output values for the associated neurons, and (ii) holding in the second memory area of each processing section input values used to calculate the second series of neuron output values for the associated neurons.

Claim 24

A method according to claim 19, wherein: the step of transmitting the addresses to the first memory area includes the step of transmitting a set if addresses to the first memory area in a given order; and the step of transmitting the addresses to the second memory area includes the step of transmitting said set of addresses to the second memory area in said given order.