Memory readback check apparatus

Claim 2

A memory check circuit for a memory system using a plurality of memories whose write addresses and read addresses are automatically updated in response to a data write and read clock pulse, respectively, comprising: means coupled to said plurality of memories for inserting a unique word for data error detection into a data sequence at predetermined intervals and for providing a unique word-inserted data sequence; write clock pulse supplying means for supplying said write clock pulse to each of said plurality of memories; read clock pulse supplying means for supplying said read clock pulse to each of said plurality of memories; said plurality of memories writing said unique word-inserted data sequence in response to said write clock pulse and reading out said unique word-inserted data sequence on a first-in-first-out basis in response to said read clock pulse to output an output data sequence; means coupled to said plurality of memories for detecting said unique word from said output data sequence and generating a detection signal; and timer means for counting a predetermined period of time and for generating a reset signal to reset said plurality of memories if said detection signal is not generated within said predetermined period of time.

Claim 3

A memory check circuit comprising: first clock pulse generating means for generating a first clock pulse for use in data writing; means for generating a selection signal at predetermined intervals in response to said first clock pulse; selecting means for selecting either input data supplied from outside or a unique word for error detection according to said selection signal; a plurality of memories connected in parallel into which the output data from said selecting means is written; means responsive to said first clock pulse for generating a write clock pulse in response to which the output data from said selecting means is written into said plurality of memories; second clock pulse generating means for generating a second clock pulse for use in data reading; means responsive to said second clock pulse for generating a read clock pulse in response to which the data written into said plurality of memories are read out; detecting means responsive to the data read out of said plurality of memories for generating a detection signal if said unique word for error detection is detected from said read-out data; timer means for measuring a predetermined period of time and for generating an error detection signal if said detection signal is not generated within said predetermined period of time; and means for generating a reset signal for said plural memories based on said error detection signal.

Claim 4

A memory check circuit comprising: first clock pulse generating means for generating a first clock pulse for use in data writing; means for generating a selection signal at predetermined intervals in response to said first clock pulse; selecting means for selecting either input data supplied from outside or a unique word for error detection according to said selection signal; a plurality of memories connected in parallel into which the output data from said selecting means is written; means responsive to said first clock pulse for generating a write clock pulse in response to which the output data from said selecting means is written into said plurality of memories; second clock pulse generating means for generating a second clock pulse for use in data reading; means responsive to said second clock pulse for generating a read clock pulse in response to which the data written into said plurality of memories are read out; detecting means responsive to the data read out of said plurality of memories for generating a detection signal if said unique word for error detection is detected from said read-out data; timer means for measuring a predetermined period of time and for generating an error detection signal if said detection signal is not generated within said predetermined period of time; and means for generating a reset signal for said plural memories based on said error detection signal.

Claim 5

A memory check circuit, as claimed in claim 1, further comprising control means for starting to count said write clock pulse when said reset signal is generated; suspending the operation of said read clock pulse supplying means until a predetermined count is reached; resuming the operation of said read clock pulse supplying means and at the same time suspending the counting of said write clock pulse when said predetermined count is reached.

Claim 6

A memory check circuit, as claimed in claim 2, further comprising control means for starting to count said write clock pulse when said reset signal is generated; suspending the operation of said second clock pulse generating circuit until a predetermined count is reached; resuming the operation of said second clock pulse generating circuit and at the same time suspending the counting of said write clock pulse when said predetermined count is reached.