Time-division switching circuit transforming data formats

Claim 1

A time-division switching circuit for exchanging a time slot with another time slot in one cycle of time-division multiplexed data, where said one cycle of data comprises a plurality of time-division multiplexed data respectively having different data formats, comprising: a first data buffer memory for holding one cycle, as aforesaid, of time-division multiplexed data; a successive address generating circuit for generating successive addresses to successively write all the time slots of each cycle of time-division multiplexed data into said first data buffer memory; an address control memory for holding addresses for reading the time slots held in said first data buffer memory, said addresses for reading being held in said address control memory in such an order so as to effect said exchange of time slots when successive addresses are applied to said address control memory for deriving therefrom the aforesaid addresses for reading as held therein; and an address setting control circuit for setting said addresses for reading into said address control memory for being held thereby, said setting of said addresses for reading being carried out so as to simultaneously perform exchanges of time slots within each time-division multiplexed data among said plurality of time-division multiplexed data, and exchanges of time slots across different time-division multiplexed data among said plurality of time-division multiplexed data for transforming a format of data in one of said different time-division multiplexed data to another format in another of said different time-division multiplexed data.