US4545052A
Expired / Lapsed
US
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Data format converter
Assignee: Nortel Networks Ltd
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Filing: 1984-01-26
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Granted: 1985-10-01
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Expires: 2004-01-26
Abstract
Abstract The conversion of bit-interleaved to byte-interleaved data is achieved using a memory and a universal shift register. The period of each bit-interleaved timeslot is divided into three parts for which corresponding timing signals are provided. During the first timing signal, the content of a memory location corresponding to an output channel is loaded into the universal shift register. During the second timing signal, the incoming bit associated with the timeslot is shifted serially into the register and during the third signal, the content of the register is returned to its original location in memory. After a frame of bit-interleaved data has been received at the register, the memory contains the corresponding frame of byte-interleaved data.
Inventors
- 👤 Herbert L. Steierman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:12
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/16; H04J3/1605; H04J3/1623; H04J3/1635; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
265 words
A circuit for converting bit-interleaved data formatted in a frame having n subframes each comprising x bits and wherein each frame consists of nx timeslots, into byte-interleaved data formatted in a frame having x channels each comprising n bits, the circuit comprising: memory means having at least one page of x locations each having at least n bits, means for generating, for each timeslot period, sequential first, second, and third timing signals, a shift register adapted to accept and output parallel and serial data and serially shift its content, means for connection to a source of said bit-interleaved data, said memory means being responsive to memory address signals and to one of said first timing signals for outputting in parallel to the shift register the content of the location corresponding to the address signals, the location corresponding to a predetermined one of said channels, the shift register also being responsive to the first timing signal for receiving the content of the memory means location and being responsive to the second timing signal of the same timeslot period as said one of said first timing signals for shifting in serially the data bit available at said connection means and being responsive to the third timing signal of the same timeslot period as said second timing signal for outputting its contents to the memory means, and the memory means being responsive to said third timing signal for writing back into said location the content of the shift register, whereby, after nx timeslots, the page of x locations of the memory means contains a frame of byte-formatted data.
Claim 2
Dependent Claim
265 words
A circuit for converting bit-interleaved data formatted in a frame having n subframes each comprising x bits and wherein each frame consists of nx timeslots, into byte-interleaved data formatted in a frame having x channels each comprising n bits, the circuit comprising: memory means having at least one page of x locations each having at least n bits, means for generating, for each timeslot period, sequential first, second, and third timing signals, a shift register adapted to accept and output parallel and serial data and serially shift its content, means for connection to a source of said bit-interleaved data, said memory means being responsive to memory address signals and to one of said first timing signals for outputting in parallel to the shift register the content of the location corresponding to the address signals, the location corresponding to a predetermined one of said channels, the shift register also being responsive to the first timing signal for receiving the content of the memory means location and being responsive to the second timing signal of the same timeslot period as said one of said first timing signals for shifting in serially the data bit available at said connection means and being responsive to the third timing signal of the same timeslot period as said second timing signal for outputting its contents to the memory means, and the memory means being responsive to said third timing signal for writing back into said location the content of the shift register, whereby, after nx timeslots, the page of x locations of the memory means contains a frame of byte-formatted data.
Claim 3
Dependent Claim
63 words
A circuit as defined in claim 1 wherein the memory means comprises at least two pages of x locations each having at least n bits and further comprising, means for marking the boundary of each incoming frame of bit-interleaved data and for alternately enabling the pages of the memory means every nx timeslots, whereby the idle page of memory may be read out.
Claim 4
Dependent Claim
57 words
The circuit as defined in claim 2 wherein the means for marking comprises a counter adapted for counting at least up to nx timeslots, the counter being reset at every frame boundary of the bit-interleaved data, the output of the counter being effective for switching from the active to the previously idle page of the memory means.
Claim 5
Independent Claim
244 words
A method of converting bit-interleaved data formatted in a frame having n subframes each comprising x bits and wherein each frame consists of nx timeslots, into byte-interleaved data formatted in a frame having x channels each comprising n bits, including a circuit comprising a memory means having at least one page of x locations each having at least n bits, a shift register adapted to accept and output parallel and serial data and serially shift its content, the register shift having a first input for connection to a source of bit-interleaved data and a second input for connection to the memory means, and means for generating and supplying timing signals to the memory means and the shift register, the method comprising the steps of: (a) generating sequential first, second and third timing signals for each timeslot period; (b) during said first timing signal of each timeslot, loading into the shift register the contents of a memory location allocated to the x channel associated with the timeslot; (c) during the second timing signal, serially shifting into the shift register, the bit from the bit-interleaved data associated with the timeslot; and (d) during the third timing signal, loading the contents of the shift register back into the memory location allocated to the x channel associated with the timeslot; whereby after nx timeslots, each location of the memory contains a byte of data and the page of x locations of memory contains a frame of byte-formatted data.
Claim 6
Independent Claim
244 words
A method of converting bit-interleaved data formatted in a frame having n subframes each comprising x bits and wherein each frame consists of nx timeslots, into byte-interleaved data formatted in a frame having x channels each comprising n bits, including a circuit comprising a memory means having at least one page of x locations each having at least n bits, a shift register adapted to accept and output parallel and serial data and serially shift its content, the register shift having a first input for connection to a source of bit-interleaved data and a second input for connection to the memory means, and means for generating and supplying timing signals to the memory means and the shift register, the method comprising the steps of: (a) generating sequential first, second and third timing signals for each timeslot period; (b) during said first timing signal of each timeslot, loading into the shift register the contents of a memory location allocated to the x channel associated with the timeslot; (c) during the second timing signal, serially shifting into the shift register, the bit from the bit-interleaved data associated with the timeslot; and (d) during the third timing signal, loading the contents of the shift register back into the memory location allocated to the x channel associated with the timeslot; whereby after nx timeslots, each location of the memory contains a byte of data and the page of x locations of memory contains a frame of byte-formatted data.
Claim 7
Dependent Claim
76 words
The method defined in claim 4 wherein the memory comprises at least two pages of x locations and the method further comprises the step of marking the boundary of each incoming frame of bit-interleaved data, and in response thereto, switching from the active to the previously idle page of memory thereby operating on alternate frames of incoming data using alternate pages of the memory means, and allowing the idle page of memory to be read out.
Claim 8
Dependent Claim
37 words
The method defined in claim 5 and further comprising the step of reading out the byte-formatted data from the idle page of memory during the period of the second timing signals of the following frame of data.
Claim 9
Dependent Claim
34 words
The method defined in claim 5 wherein the step of marking is achieved by initiating a timeslot counter at the beginning of each incoming frame of bit-interleaved data and resetting it every nx timeslot.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-30 | 1989-04-01 | 1989-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-30 | 1993-04-01 | 1993-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-30 | 1997-04-01 | 1997-10-01 | $7700.00 | Window Closed / Lapsed |