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US4972103A Expired / Lapsed US ⏱️ 0.0 years remaining

Accelerated switching input circuit

Assignee: US Philips Corp
•
Filing: 1989-07-28
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Granted: 1990-11-20
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Expires: 2009-07-28
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Abstract

Abstract An accelerated switching input circuit includes an emitter coupled logic stage having two transistors. The first transistor receives at its base an input signal and the second transistor receives at its base a control signal generated from the signal at the collector of the first transistor. A third transistor (T 6 ) has its base connected to the collector of the first transistor (T 3 ). A first resistor (R 10 ), a second resistor (R 11 ) and a third resistor (R 12 ) are disposed in series between the emitter of the third transistor and a reference voltage (U REF ) source. The point B common to the resistors R 11 and R 12 is coupled to the base of the second transistor (T 4 ).

Inventors

  • 👤 Stephane Barbu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 03:50
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/2893

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 189 words
Switching input circuit comprising: a stage of the emitter coupled logic (ECL) type having first and second transistors, the first transistor receiving at its base an input signal and the second transistor receiving at its base a control signal which is generated by a control circuit responsive to a signal from a collector of the first transistor, in order to obtain at a collector of the second transistor an output signal switching faster than the input signal, wherein the control circuit comprises a third transistor whose collector is connected to a voltage supply source and whose base is connected to the collector of the first transistor, a first resistor, a second resistor and a third resistor connected in series between an emitter of the third transistor and a reference point to which is connected a reference voltage source and a first reference current source, means connecting a point common to the first resistor and the second resistor to a second reference current source, and a point common to the second resistor and the third resistor supplying said control signal and being connected to the base of the second transistor.
Claim 2
Dependent Claim 189 words
Switching input circuit comprising: a stage of the emitter coupled logic (ECL) type having first and second transistors, the first transistor receiving at its base an input signal and the second transistor receiving at its base a control signal which is generated by a control circuit responsive to a signal from a collector of the first transistor, in order to obtain at a collector of the second transistor an output signal switching faster than the input signal, wherein the control circuit comprises a third transistor whose collector is connected to a voltage supply source and whose base is connected to the collector of the first transistor, a first resistor, a second resistor and a third resistor connected in series between an emitter of the third transistor and a reference point to which is connected a reference voltage source and a first reference current source, means connecting a point common to the first resistor and the second resistor to a second reference current source, and a point common to the second resistor and the third resistor supplying said control signal and being connected to the base of the second transistor.
Claim 3
Dependent Claim 33 words
A circuit according to claim 1, wherein the reference voltage source comprises a fourth transistor whose collector is connected to the voltage supply source and whose base is connected to a reference voltage.
Claim 4
Dependent Claim 32 words
A circuit according to claim 2, which comprises at least one forward biased diode connected between the emitter of the third transistor (R 10 ) and the first resistor (R 10 ).
Claim 5
Dependent Claim 26 words
A circuit according to claim 1, which comprises at least one forward biased diode connected between the emitter of the third transistor and the first resistor.

References Cited (Backward Citations)

US3558914A Cited
US3646361A Cited
US3694198A Cited
US4629913A Cited
JPS62264909A Cited
US4835455A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-11-19 1994-05-21 1994-11-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-11-19 1998-05-21 1998-11-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-11-19 2002-05-21 2002-11-20 $7700.00 Window Closed / Lapsed

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