Patent US3719915A successfully refreshed from Google Patents.
Patent US4969117A successfully refreshed from Google Patents.
US4969117A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chaining and hazard apparatus and method
Assignee: KUBOTA USA Inc
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Filing: 1989-05-05
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Granted: 1990-11-06
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Expires: 2009-05-05
Abstract
Abstract An apparatus and method for detecting data conflicts in a multiple processor computer system and for throttling processing of instructions in individual pipelines where data conflicts exist. The present invention comprises circuitry for detecting data conflict problems in a computer system. The circuit of the present invention comprises a plurality of registers associated with each processor in the system. The registers are used to store a range of elements to be written by the associated processor and a plurality of ranges of elements to be read by the associated processor. These ranges are then compared against data accesses by other processors in the computer system and where a data conflict exists, a circuit is provided for determining which processor will be allowed to continue processing and which processor will be prevented from continuing processing. The circuitry ensures the processor completes processing of instructions in a logical manner giving expected results while allowing maximal element level overlap.
Inventors
- 👤 Glen S. Miranker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:25
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/3834; G06F9/3836; G06F9/3838
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
130 words
A circuit for detecting data conflicts in a computer system, said circuit comprising: a first storing means for storing a first address, said first address corresponding to a beginning address in a range of addresses to be written by a first processor; a second storing means for storing a second address, said second address corresponding to an ending address in a range of addresses to be written by said first processor; a third storing means for storing a third address, said third address corresponding to an element to be written by a second processor; a first comparator means for comparing said first address and said second address to said third address, said first comparator means coupled with said first storing means, said second storing means and said third storing means.
Claim 2
Dependent Claim
130 words
A circuit for detecting data conflicts in a computer system, said circuit comprising: a first storing means for storing a first address, said first address corresponding to a beginning address in a range of addresses to be written by a first processor; a second storing means for storing a second address, said second address corresponding to an ending address in a range of addresses to be written by said first processor; a third storing means for storing a third address, said third address corresponding to an element to be written by a second processor; a first comparator means for comparing said first address and said second address to said third address, said first comparator means coupled with said first storing means, said second storing means and said third storing means.
Claim 3
Dependent Claim
26 words
The circuit as recited by claim 1, further comprising a means for determining order of processing of instructions in said first processor and said second processor.
Claim 4
Dependent Claim
40 words
The circuit as recited by claim 2, further comprising an AND gate, said AND gate having as inputs an output signal from said first comparator means and an output signal from said means for determining order of processing of instructions.
Claim 5
Dependent Claim
38 words
The circuit as recited by claim 3, further comprising an OR gate, said OR gate coupled with said AND gate as one input, said OR gate providing an output indicating whether processing may continue on said second processor.
Claim 6
Dependent Claim
62 words
The circuit as recited by claim 4, wherein said means for determining order of processing of instructions comprises an S-R flip-flop, said S-R flip-flop having as an S input a signal indicating processing is beginning on a new instruction in said second processor and as an R input a signal indicating processing is beginning on a new instruction in said first processor.
Claim 7
Dependent Claim
147 words
In a computer system having a first processing means for processing a first instruction and a second processing means for processing a second instruction, said first instruction causing said first processor to write a first vector, said first vector having a beginning element with an address Xl and an ending element with an address Y1, said second instruction causing said second processor to write a second element, said second element having an address Al, a method for preventing data conflicts comprising the steps of: (a) determining if said address A1 falls in a range of addresses bounded addresses X1 and Y1; (b) if said address A1 falls in said range of addresses, determining if said first instruction was issued prior to said second instruction being issued; (c) if said first instruction was issued prior to said second instruction, preventing said second processor from writing said second element.
Claim 8
Dependent Claim
147 words
In a computer system having a first processing means for processing a first instruction and a second processing means for processing a second instruction, said first instruction causing said first processor to write a first vector, said first vector having a beginning element with an address Xl and an ending element with an address Y1, said second instruction causing said second processor to write a second element, said second element having an address Al, a method for preventing data conflicts comprising the steps of: (a) determining if said address A1 falls in a range of addresses bounded addresses X1 and Y1; (b) if said address A1 falls in said range of addresses, determining if said first instruction was issued prior to said second instruction being issued; (c) if said first instruction was issued prior to said second instruction, preventing said second processor from writing said second element.
References Cited (Backward Citations)
GB1397310A
Cited
GB1570510A
Cited
GB1582815A
Cited
US4339808A
Cited
US4532589A
Cited
GB2113878A
Cited
GB2159309A
Cited
US4594655A
Cited
EP0121700A2
Cited
US4777593A
Cited
GB2153558A
Cited
US4777592A
Cited
US4789925A
Cited
US4768148A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-05 | 1994-05-07 | 1994-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-05 | 1998-05-07 | 1998-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-05 | 2002-05-07 | 2002-11-06 | $7700.00 | Window Closed / Lapsed |