Patent US4965724A successfully refreshed from Google Patents.
US4965724A
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Compiler system using reordering of microoperations to eliminate interlocked instructions for pipelined processing of assembler source program
Assignee: Oki Electric Industry Co Ltd
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Filing: 1988-02-29
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Granted: 1990-10-23
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Expires: 2008-02-29
Abstract
Abstract A compiler system compiles a source program described with assembler instructions, each of which defines microoperations, into a target program for use in a digital signal processor. If two of the assembler instructions are interlocked with each other and if another assembler instructions which is not associated with the interlocked instructions is present, it is inserted between the interlocked instructions to thereby reorder the microoperations of the source program. Thereafter, the microoperations thus reordered are combined so as not to conflict with each other with regard to the fields of the assembler instructions and resources used by the assembler instructions. Prior to combining the microoperations, whether or not a basic block of assembler instructions included in the source program having a loop may be determined. If so, a head portion of the basic block forming the loop may then be transferred to a tail portion of the basic block forming the loop.
Inventors
- 👤 Isao Utsumi
- 👤 Yoshikazu Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:35
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/40; G06F8/41; G06F8/44; G06F8/445
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
244 words
A method of compiling a source program described with assembler instructions, each of which defines a plurality of microoperations, into a target program for use in a pipeline processor operative with microcodes forming a horizontal type of instructions defined by the microoperations, comprising the steps of: (a) reading the source program and generating intermediate codes representative of the assembler instructions; (b) identifying basic blocks of the intermediate codes of the assembler instructions and determining whether or not any basic block forms a loop, each basic block having a respective head portion and tail portion, and calculating a Du-chain for the basic blocks; (c) transferring either of the head and tail portions of a basic block forming a loop, if any, to the remaining one of the head and tail portions of the basic block forming the loop, the portion to be transferred being determined on the basis of a live parameter, included in the basic block immediately following the basic block forming the loop, resulting from the calculated Du-chain; (d) reordering microoperations of said source program by determining whether or not two of the assembler instructions are interlocked with each other, and placing another of the assembler instructions which is independent of the interlocked assembler instructions between the interlocked assembler instructions, if any; and (e) combining the microoperations reordered in said reordering step so as not to conflict with each other on fields of the assembler instructions and resources used by the assembler instructions.
Claim 2
Independent Claim
244 words
A method of compiling a source program described with assembler instructions, each of which defines a plurality of microoperations, into a target program for use in a pipeline processor operative with microcodes forming a horizontal type of instructions defined by the microoperations, comprising the steps of: (a) reading the source program and generating intermediate codes representative of the assembler instructions; (b) identifying basic blocks of the intermediate codes of the assembler instructions and determining whether or not any basic block forms a loop, each basic block having a respective head portion and tail portion, and calculating a Du-chain for the basic blocks; (c) transferring either of the head and tail portions of a basic block forming a loop, if any, to the remaining one of the head and tail portions of the basic block forming the loop, the portion to be transferred being determined on the basis of a live parameter, included in the basic block immediately following the basic block forming the loop, resulting from the calculated Du-chain; (d) reordering microoperations of said source program by determining whether or not two of the assembler instructions are interlocked with each other, and placing another of the assembler instructions which is independent of the interlocked assembler instructions between the interlocked assembler instructions, if any; and (e) combining the microoperations reordered in said reordering step so as not to conflict with each other on fields of the assembler instructions and resources used by the assembler instructions.
Claim 3
Dependent Claim
29 words
A method in accordance with claim 1 further comprising the step of generating microinstructions including with the microoperations combined in said combining step to thereby produce the target program.
References Cited (Backward Citations)
US4398249A
Cited
US4468736A
Cited
US4567574A
Cited
US4656583A
Cited
US4763255A
Cited
US4656582A
Cited
US4802091A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |