Firmware state apparatus for controlling sequencing of processing including test operation in multiple data lines of communication

Claim 2

A firmware state apparatus for controlling data transfer between a communication system having multiple independent data lines and a computer system, said apparatus comprising; a transmit processor and a receive processor, a processor memory coupled to said transmit processor and said receive processor and having a plurality of firmware instructions for performing data transfer between each of said lines of the communication system and the computer system, said instructions being divided into a plurality of groups that establish a corresponding number of predefined states so that a transition from one state to another state is executed within a period of time which is small in comparison to the amount of time for servicing all of said lines, predetermined groups of instructions including at least one instruction defining a test operation for evaluating a condition related to one of said lines to control sequencing to a next one of the predefined states, a shared memory having a plurality of locations for line table information for said lines, said shared memory containing an address specifying a starting instruction of one of said groups of instructions, one of said processors, in response to a group of instructions performing a designated operation, and in response to said instruction defining a test operation as a function of said condition, accessing in said shared memory a starting address of another group of instructions, and control means for enabling conflict-free access to said shared memory by said transmit processor and said receive processor.

Claim 3

A firmware state apparatus as set forth in claim 1 wherein said one of said processors has a program counter and said at least one location of said shared memory contains a program counter address.

Claim 4

A firmware state apparatus as set forth in claim 1 wherein all of said predefined states are common to all data lines and wherein said groups of instructions are executed so that each data line utilizes the same predefined states.

Claim 5

A firmware state apparatus as set forth in claim 1 wherein said predetermined ones of said groups of instructions include, at a predetermined point, at least one instruction defining a suspend operation.

Claim 6

A firmware state apparatus as set forth in claim 4 wherein said one of said processors suspends operation on one line in response to said instruction defining a suspend operation for enabling said one of said processors to serve another line.

Claim 7

A firmware state apparatus as set forth in claim 5 wherein said suspend operation is defined by multiple instructions.

Claim 8

A firmware state apparatus as set forth in claim 4 further including additional instructions in predetermined groups of instructions for carrying out work tasks for enabling data transfer between said communication system and said computer system.

Claim 9

A firmware state apparatus as set forth in claim 1 wherein said processor memory comprises a programmable read only memory.

Claim 10

A firmware state apparatus as set forth in claim 1 wherein said shared memory has line table information for all data lines stored separately on a line-by-line basis.

Claim 11

A firmware state apparatus as set forth in claim 9 including means for controlling said one of said processors to access only one line table at a time in a predetermined sequence in which all lines are accessed.

Claim 12

A firmware state apparatus as set forth in claim 10 wherein each line table contains an address identified as a suspend address representative of the predefined state to be returned to upon attaining access to that data line again.

Claim 13

A firmware state apparatus as set forth in claim 1 wherein predetermined groups of instructions include at least one instruction for loading the starting address of a group of instructions into said one of said processors.

Claim 14

A firmware state apparatus as set forth in claim 1 wherein said predetermined groups of instructions include at least one instruction defining a suspend operation to carry out the suspending of operation on one line in response to said at least one instruction for enabling said one of said processors to return to said same line at a later time.

Claim 15

A firmware state machine as set forth in claim 1 wherein said predetermined groups of instructions include at least one instruction defining a suspend operation to carry out the suspending of operation on one line in response to said at least one instruction for enabling said one of said processors to service another line at a later time.

Claim 18

A method of controlling data transfer as set forth in claim 15 wherein said predetermined groups of instructions include, at a predetermined point, at least one instruction defining a suspend operation.

Claim 19

A method of controlling data transfer as set forth in claim 16 including controlling said one of said processors to suspend operation on one line in response to said at least one instruction defining a suspend operation for enabling said one of said processors to serve another line.

Claim 20

A method of controlling data transfers as set forth in claim 17 wherein said suspend operation is defined by multiple instructions.

Claim 21

A method of controlling data transfer as set forth in claim 17 including providing instructions in said predetermined groups of instructions for carrying out work tasks for enabling data transfer between said telephone communication system and said computer system.

Claim 22

A method of controlling data transfer as set forth in claim 15 wherein said predetermined groups of instructions include at least one instruction for loading the starting address of a group of instructions into said one of said processors.

Claim 23

A method of controlling data transfer as set forth in claim 15 wherein said predetermined groups of instructions include at least one instruction defining a suspend operation to carry out the suspension of operation on one line in response to said instruction for enabling said one of said processors to return to said same line at a later time.

Claim 24

A method of controlling data transfer as set forth in claim 15 wherein said predetermined groups of instructions include at least one instruction defining a suspend operation to carry out the suspension of operation on one line in response to said instruction for enabling said one of said processors to service another line at a later time.

Claim 25

A state machine for controlling data transfer between a communication system including multiple independent lines and a computer system, said state machine comprising: first memory means including a receive memory section containing a receive instruction sequence for controlling data transfer from said lines to said computer system and a transmit memory section containing a transmit instruction sequence for controlling data transfer from said computer system to said lines, said receive and transmit instruction sequences each including a plurality of suspend operations at predetermined locations therein; second memory means including multiple line tables, one for each of said lines, each line table including a location for storing a suspend address; and processor means for executing one of said instruction sequences for a first one of said lines until a suspend operation is encountered, including means responsive to the suspend operation for storing a suspend address in the suspend address location of the line table for said first one of said lines, for accessing the suspend address in the line table for a next one of said lines, and for resuming execution of said instruction sequence at the suspend address specified in the line table for the next one of said lines, said processor means including a receive processor for executing said receive instruction sequence and a transmit processor for executing said transmit instruction sequence, said second memory means being shared by said receive processor and said transmit processor, said state machine further including control means for enabling conflict-free access to said second memory means by said receive processor and said transmit processor, whereby said state machine controls data transfer one each of said lines without having to respond to interrupts.

Claim 26

A state machine for controlling data transfer between a communication system including multiple independent lines and a computer system, said state machine comprising: first memory means including a receive memory section containing a receive instruction sequence for controlling data transfer from said lines to said computer system and a transmit memory section containing a transmit instruction sequence for controlling data transfer from said computer system to said lines, said receive and transmit instruction sequences each including a plurality of suspend operations at predetermined locations therein; second memory means including multiple line tables, one for each of said lines, each line table including a location for storing a suspend address; and processor means for executing one of said instruction sequences for a first one of said lines until a suspend operation is encountered, including means responsive to the suspend operation for storing a suspend address in the suspend address location of the line table for said first one of said lines, for accessing the suspend address in the line table for a next one of said lines, and for resuming execution of said instruction sequence at the suspend address specified in the line table for the next one of said lines, said processor means including a receive processor for executing said receive instruction sequence and a transmit processor for executing said transmit instruction sequence, said second memory means being shared by said receive processor and said transmit processor, said state machine further including control means for enabling conflict-free access to said second memory means by said receive processor and said transmit processor, whereby said state machine controls data transfer one each of said lines without having to respond to interrupts.

Claim 27

A state machine as defined in claim 23 wherein said control means includes means for time multiplexing access to said second memory means by said receive processor and said transmit processor.

Claim 28

A state machine as defined in claim 24 wherein said receive memory section and said transmit memory section comprise separate read only memories coupled to said receive processor and said transmit processor, respectively.

Claim 29

A state machine as defined in claim 24 wherein said control means includes means for causing said receive processor to service said lines in a first predetermined sequence and for causing said transmit processor to service said lines in a second predetermined sequence different from said first predetermined sequence.

Claim 30

A state machine as defined in claim 24 wherein each of said suspend operations includes at least one instruction in the respective instruction sequence.

Claim 33

A method for controlling data transfer as defined in claim 28 including the step of repeating steps (c) to (f) until all of said lines have been serviced.

Claim 34

A method for controlling data transfer as defined in claim 28 wherein the step of enabling conflict-free access includes time multiplexing access to said line tables by said receive processor and said transmit processor during execution of said receive instruction sequence and said transmit instruction sequence.

Claim 35

A method for controlling data transfer as defined in claim 30 further including the steps of said receive processor servicing said lines in a first predetermined sequence, and said transmit processor servicing said lines in a second predetermined sequence different from said first predetermined sequence.

Claim 36

A method for controlling data transfer as defined in claim 28 further including the step of selecting the predetermined locations of said suspend operations such that all of said lines are serviced without excessive delay.

Claim 37

A state machine for controlling data transfer between a communication system including multiple independent lines and a computer system, said state machine comprising: a receive memory section containing a receive instruction sequence for controlling data transfer from said lines to said computer system; a transmit memory section containing a transmit instruction sequence for controlling data transfer from said computer system to said lines, said receive and transmit instruction sequences each including a plurality of suspend operations at predetermined locations therein; a shared memory including multiple line tables, one for each of said lines, each line table including a location for storing a receive suspend address and a transmit suspend address; a receive processor for executing said receive instruction sequence for one of said lines until a suspend operation is encountered, said receive processor including means responsive to a suspend operation for storing a receive suspend address in the suspend address location of the line table for said one of said lines; a transmit processor for executing said transmit instruction sequence for a different one of said lines until a suspend operation is encountered, said transmit processor including means responsive to a suspend operation for storing a transmit suspend address in the suspend address location of the line table for said different one of said lines, said receive processor and said transmit processor each including means for accessing the respective suspend address in the line table for a next one of said lines and for resuming execution of the respective instruction sequence at the suspend address specified in the line table for the next one of said lines; and control means for enabling conflict-free access to said shared memory by said receive processor and said transmit processor, whereby said state machine controls data transfer on each of said lines without having to respond to interrupts.

Claim 38

A state machine for controlling data transfer between a communication system including multiple independent lines and a computer system, said state machine comprising: a receive memory section containing a receive instruction sequence for controlling data transfer from said lines to said computer system; a transmit memory section containing a transmit instruction sequence for controlling data transfer from said computer system to said lines, said receive and transmit instruction sequences each including a plurality of suspend operations at predetermined locations therein; a shared memory including multiple line tables, one for each of said lines, each line table including a location for storing a receive suspend address and a transmit suspend address; a receive processor for executing said receive instruction sequence for one of said lines until a suspend operation is encountered, said receive processor including means responsive to a suspend operation for storing a receive suspend address in the suspend address location of the line table for said one of said lines; a transmit processor for executing said transmit instruction sequence for a different one of said lines until a suspend operation is encountered, said transmit processor including means responsive to a suspend operation for storing a transmit suspend address in the suspend address location of the line table for said different one of said lines, said receive processor and said transmit processor each including means for accessing the respective suspend address in the line table for a next one of said lines and for resuming execution of the respective instruction sequence at the suspend address specified in the line table for the next one of said lines; and control means for enabling conflict-free access to said shared memory by said receive processor and said transmit processor, whereby said state machine controls data transfer on each of said lines without having to respond to interrupts.

Claim 39

A state machine as defined in claim 33 wherein said control means includes means for time multiplexing access to said shared memory by said receive processor and said transmit processor.

Claim 40

A state machine as defined in claim 34 wherein said control means includes means for causing said receive processor to service said lines in a first predetermined sequence and for causing said transmit processor to service said lines in a second predetermined sequence different from said first predetermined sequence.