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US4965649A Expired / Lapsed US ⏱️ 0.0 years remaining

Manufacture of monolithic infrared focal plane arrays

Assignee: Lockheed Martin Tactical Systems Inc
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Filing: 1989-10-05
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Granted: 1990-10-23
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Expires: 2009-10-05
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Abstract

Abstract The manufacture of monolithic HgCdTe detectors and Si circuitry in an IR focal plane array is achieved by forming a protective layer of SiO 2 or SiN x on a silicon wafer containing silicon circuits, etching steep-wall recesses into the wafer, selectively depositing epitaxial single-crystal layers of GaAs, CdTe, and HgCdTe in the recesses fabricating HgCdTe IR arrays, and depositing appropriate insulating and conductive interconnection patterns to interconnect the Si devices with one another and the HgCdTe devices with the Si devices. Little or no GaAs, CdTe, and HgCdTe grows on the SiO 2 or SiN x outside the recesses. Since material grown outside the recess is polycrystalline, it is easily chemomechanically removed.

Inventors

  • 👤 Ken Zanio
  • 👤 Ross C. Bean

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 19:40
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/18; H10F39/184; H10F39/1843

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 86 words
A monolithic focal plane array structure including interconnected silicon circuitry and HgCdTe detectors, comprising: (a) a silicon substrate having silicon signal readout device circuitry formed therein; (b) said substrate having recesses formed therein, said recesses being filled with monocrystalline layers of GaAs, CdTe, and HgCdTe formed on top of one another, the surface of said HgCdTe layer being substantially level with the surface of said silicon substrate; and (c) patterns of insulating material and metallic interconnectors superimposed upon said substrate surface and said HgCdTe layer surface.
Claim 2
Dependent Claim 86 words
A monolithic focal plane array structure including interconnected silicon circuitry and HgCdTe detectors, comprising: (a) a silicon substrate having silicon signal readout device circuitry formed therein; (b) said substrate having recesses formed therein, said recesses being filled with monocrystalline layers of GaAs, CdTe, and HgCdTe formed on top of one another, the surface of said HgCdTe layer being substantially level with the surface of said silicon substrate; and (c) patterns of insulating material and metallic interconnectors superimposed upon said substrate surface and said HgCdTe layer surface.

References Cited (Backward Citations)

US4228365A Cited
US4276099A Cited
US4553152A Cited
US4588451A Cited
US4689650A Cited
US4904607A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-10-22 1994-04-23 1994-10-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-10-22 1998-04-23 1998-10-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-10-22 2002-04-23 2002-10-23 $7700.00 Window Closed / Lapsed

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