US4965577A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device having a wiring layout to avoid intersections between analog signal wiring layers and digital signal wiring layers
Assignee: Hitachi Ltd
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Filing: 1986-04-08
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Granted: 1990-10-23
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Expires: 2006-04-08
Abstract
Abstract A semiconductor circuit is constructed of a digital signal input circuit and an analog signal input circuit to be fed with an analog signal through a multiplexer. An analog signal wiring layer to be coupled to the input terminal of the analog signal input circuit is made not to intersect any digital signal wiring layer. As a result, an undesirable coupling capacitance to be formed by the intersecting wiring layers, if any, is not coupled to the analog signal wiring layer. Because of the absence of the undesirable coupling capacitance it is possible to substantially reduce the crosstalk of the digital signal from the digital signal wiring layer to the analog signal wiring layer.
Inventors
- 👤 Shiro Baba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:50
CPC Classifications
H; H10; H10D; H10D99/00; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
196 words
A semiconductor integrated circuit device comprising: an analog signal transmission link formed on a semiconductor substrate in a first prescribed geometrical pattern; a first prescribed, analog signal-handling, electronic circuit formed on said substrate and coupled to said analog signal transmission link so that analog signals may be exchanged between said first prescribed circuit and said analog signal transmission link; a digital transmission link formed on said substrate in a second prescribed geometrical pattern separated from said first prescribed geometrical pattern so as not to overlap said first pattern; a second prescribed, digital signal-handling, electronic circuit formed on said substrate and coupled to said digital signal transmission link so that digital signals may be exchanged between said second prescribed circuit and said digital signal transmission link; and at least one bonding pad electrode formed on said substrate at a position thereof separating said analog signal transmission link from said digital signal transmission link, wherein said bonding pad electrode is arranged adjacent a peripheral portion of said substrate, and wherein said analog transmission link has a portion which is disposed along said peripheral portion of said substrate between an edge of said substrate and said bonding pad electrode.
Claim 2
Dependent Claim
196 words
A semiconductor integrated circuit device comprising: an analog signal transmission link formed on a semiconductor substrate in a first prescribed geometrical pattern; a first prescribed, analog signal-handling, electronic circuit formed on said substrate and coupled to said analog signal transmission link so that analog signals may be exchanged between said first prescribed circuit and said analog signal transmission link; a digital transmission link formed on said substrate in a second prescribed geometrical pattern separated from said first prescribed geometrical pattern so as not to overlap said first pattern; a second prescribed, digital signal-handling, electronic circuit formed on said substrate and coupled to said digital signal transmission link so that digital signals may be exchanged between said second prescribed circuit and said digital signal transmission link; and at least one bonding pad electrode formed on said substrate at a position thereof separating said analog signal transmission link from said digital signal transmission link, wherein said bonding pad electrode is arranged adjacent a peripheral portion of said substrate, and wherein said analog transmission link has a portion which is disposed along said peripheral portion of said substrate between an edge of said substrate and said bonding pad electrode.
Claim 3
Dependent Claim
40 words
A semiconductor integrated circuit device according to claim 1, further comprising: first means for coupling said digital signal transmission link to said bonding pad electrode; and second means for selectively coupling said bonding pad electrode to said analog transmission link.
Claim 4
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 2, wherein said second means includes a field effect transistor.
Claim 5
Dependent Claim
19 words
A semiconductor integrated circuit device according to claim 3, wherein said first prescribed electronic circuit comprises an analog-to-digital converter.
Claim 6
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 4, wherein said second prescribed electronic circuit comprises a digital signal input circuit.
Claim 7
Dependent Claim
19 words
A semiconductor integrated circuit device according to claim 1, wherein said first prescribed electronic circuit comprises an analog-to-digital converter.
Claim 8
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 6, wherein said second prescribed electronic circuit comprises a digital signal input circuit.
Claim 9
Dependent Claim
197 words
A microprocessor comprising: an analog signal transmission link formed on a semiconductor substrate in a first prescribed geometrical pattern; a first prescribed, analog signal-handling, electronic circuit formed on said substrate and coupled to said analog signal transmission link so that analog signals may be exchanged between said first prescribed circuit and said analog signal transmission link; a digital signal transmission link formed on said substrate in a second prescribed geometrical pattern so as not to overlap said first pattern; a second prescribed, digital signal-handling, electronic circuit formed on said substrate and coupled to said digital signal transmission link so that digital signals may be exchanged between said second prescribed circuit and said digital signal transmission link; at least one bonding pad electrode formed on said substrate at a position thereof separating said analog signal transmission link from said digital signal transmission link; and an internal bus coupled to said first prescribed electronic circuit, wherein said bonding pad electrode is arranged adjacent a peripheral portion of said substrate, and wherein said analog transmission link has a portion which is disposed along said peripheral portion of said substrate between an edge of said substrate and said bonding pad electrode.
Claim 10
Dependent Claim
197 words
A microprocessor comprising: an analog signal transmission link formed on a semiconductor substrate in a first prescribed geometrical pattern; a first prescribed, analog signal-handling, electronic circuit formed on said substrate and coupled to said analog signal transmission link so that analog signals may be exchanged between said first prescribed circuit and said analog signal transmission link; a digital signal transmission link formed on said substrate in a second prescribed geometrical pattern so as not to overlap said first pattern; a second prescribed, digital signal-handling, electronic circuit formed on said substrate and coupled to said digital signal transmission link so that digital signals may be exchanged between said second prescribed circuit and said digital signal transmission link; at least one bonding pad electrode formed on said substrate at a position thereof separating said analog signal transmission link from said digital signal transmission link; and an internal bus coupled to said first prescribed electronic circuit, wherein said bonding pad electrode is arranged adjacent a peripheral portion of said substrate, and wherein said analog transmission link has a portion which is disposed along said peripheral portion of said substrate between an edge of said substrate and said bonding pad electrode.
Claim 11
Dependent Claim
37 words
A microprocessor according to claim 8, further comprising: first means for coupling said digital signal transmission link to said bonding pad electrode; and second means for selectively coupling said bonding pad electrode to said analog transmission link.
Claim 12
Dependent Claim
15 words
A microprocessor according to claim 9, wherein said second means includes a field effect transistor.
Claim 13
Dependent Claim
16 words
A microprocessor according to claim 9, wherein said first prescribed electronic circuit comprises an analog-to-digital converter.
Claim 14
Dependent Claim
18 words
A microprocessor according to claim 11, wherein said second prescribed electronic circuit comprises a digital signal input circuit.
Claim 15
Dependent Claim
27 words
A microprocessor according to claim 11, wherein said first prescribed electronic circuit comprise means for selectively coupling an output of said analog-to-digital converter to said internal bus.
Claim 16
Dependent Claim
18 words
A microprocessor according to claim 13, wherein said bonding pad electrode comprises a plurality of bonding pad electrodes.
Claim 17
Dependent Claim
25 words
A microprocessor according to claim 14, wherein said second means selectively couples selected ones of said bonding pad electrodes to said analog signal transmission link.
Claim 18
Dependent Claim
34 words
A microprocessor according to claim 15, wherein said second means includes a plurality of selectively controlled field effect transistors disposed between respective ones of said bonding pad electrodes and said analog signal transmission link.
References Cited (Backward Citations)
US3849775A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |