Ac analog to digital converter

Claim 2

An AC analog to digital converter for converting input data comprising an AC analog voltage to a digital number proportional to the amplitude of the AC analog voltage, comprising: zero crossing detector means producing an output in response to each zero crossing of the AC analog voltage, integrating means, input switching means and clearing switching means associated with said integrator, switching logic means receiving the outputs of said detector means and responsive to a first zero crossing detector output to produce an output for closing said input switching means for supply of the AC analog voltage to said integrating means and to a next successive detector output to produce an output for opening said input switching means, defining there between a data integrating interval, comparator means responsive to the integrated output voltage of said integrating means to indicate the sign and amplitude of the integrated output voltage of the integrating means, control logic responsive to the output of said switching logic means produced in response to the said next successive detector output concluding the data integration interval, to initiate a reference integration interval, said control logic responding to the sign indication of said comparator means for supply of a DC reference voltage to said integrating means of predetermined amplitude and of opposite polarity to the sign indication, a counter, said control logic gating clock pulses of a predetermined repetition rate to said counter during the reference integration interval and responding to the zero voltage indication output of said comparator for concluding the reference integration interval and terminating the gating of further clock pulses to said Counter and the supply of the DC reference voltage to said integrating means, the count attained by said counting means during the reference integration interval comprising a digital number proportional to the amplitude of the AC analog voltage for the half-cyle thereof integrated during the data integration interval, and wherein said reference voltages comprise DC compensated reference voltages of equal amplitude and opposite polarity produced from an AC reference voltage by a compensating circuit comprising: further integrating means, further input switching means operated by said switching logic to be closed for the duration of the data integration interval for supply of the AC reference voltage to said further integrating means, and to be open for the reference voltage integrating interval, and holding switch means connected between the input of said further integrating means and ground and normally in an open position and closed by said logic switching means to maintain the DC integrated voltage output of said further integrating means for the reference integration interval of said integrating means of said converter, thereby to provide a DC reference voltage output compensated for variations in the AC reference supply voltage, and an inverter receiving the output of said further integrating means for supplying the compensated DC reference voltage of the opposite polarity.

Claim 3

A synchro to digital converter for use with a synchro having a rotor winding and X, Y and Z stator windings, said rotor winding being energized by an AC reference voltage and said stator windings producing X-Y and Y-Z AC analog outputs proportional to the angular position of the rotor, comprising first and second integrating means, first and second input switching means and first and second clearing switching means associated with said first and second integrating means, respectively, a zero crossing detector responsive to the AC reference voltage and producing an output in response to each zero crossing thereof, switching logic means receiving the outputs of said zero crossing detector and responsive to a first zero crossing detector output thereof to close said first and second input switching means for supply of the X-Y and Y-Z AC analog voltages to said first and second integrating means, respectively, and responsive to a next successive zero crossing detector output to open said first and second input switching means, defining thereby between the closing and opening of each said input switching means a data integrating intervals for each said integrating means, each said integrating means producing as an output a DC voltage proportional to the magnitude of the respective AC input analog voltage, comparator means responsive to the integrated output voltage of said integrating means to indicate the sign and amplitude of the integrated output voltage of each said integrating means, control logic responsive to the output of said switching logic means corresponding to the said next successive detector output concluding the data integration interval, to initiate a reference integration interval, said control logic responding to the sign indication of said comparator means for supply of a DC reference voltage to each said integrating means of predetermined amplitude and of opposite polarity to the sign indication of the integrated output voltage of the respective integrating means produced thereby in the preceding data integration interval, for integration by said respective integrating means to reduce the respective DC integrated voltage outputs thereof to zero value, the respective intervals of reference voltage integration of said first and second integrating means varying in duration as a function of the respective values of the DC integrated output voltages thereof, first and second counters respectively associated with said first and second integrating means, and said control logiC gating clock pulses of a predetermined repetition rate to each said first and second counters during the respective reference integration intervals thereof and said control logic responding to the zero voltage indication output of said comparator for the respective integrating means to conclude the respective reference integration intervals of the first and second integrating means, to terminate the gating of further clock pulses to the corresponding counters and the supply of the respective DC reference voltages to said corresponding integrating means, each counter producing at the conclusion of the reference integration interval a count output comprising a digital number proportional to the amplitude of the corresponding one of the X-Y and Y-Z analog output voltages for the half-cycle thereof integrated during the preceding data integration interval, said switching logic means closing said first and second clearing switching means at the conclusion of the reference integration interval of the respective first and second integrating means, respectively, to clear the respective integrating means and opening said clearing switching means at the initiation of a successive data integration interval, and wherein, said reference voltages comprise DC compensated reference voltages of equal amplitude and opposite polarity, produced by a compensating circuit in response to the AC reference voltage supplied to the rotor winding of the synchro, comprising: further integrating means, further means operable for the duration of the data integration interval for supply of the AC reference voltage to said further integrating means, and holding means for maintaing the DC integrated voltage output of said further integrating means, developed during the data integration interval, for the duration of the succeeding reference integration interval of said integrating means of said converter, thereby to provide a DC voltage reference output compensated for variations in the AC reference supply voltage, and an inverter receiving the output of said further integrating means for supplying the DC compensated reference voltage of the opposite polarity.

Claim 4

A synchro to digital converter for use with a synchro having a rotor winding and X, Y and Z stator windings, said rotor winding being energized by an AC reference voltage and said stator windings producing X-Y and Y-Z AC analog outputs proportional to the angular position of the rotor, comprising first and second integrating means, first and second input switching means and first and second clearing switching means associated with said first and second integrating means, respectively, a zero crossing detector responsive to the AC reference voltage and producing an output in response to each zero crossing thereof, switching logic means receiving the outputs of said zero crossing detector and responsive to a first zero crossing detector output thereof to close said first and second input switching means for supply of the X-Y and Y-Z AC analog voltages to said first and second integrating means, respectively, and responsive to a next successive zero crossing detector output to open said first and second input switching means, defining thereby between the closing and opening of each said input switching means a data integrating intervals for each said integrating means, each said integrating means producing as an output a DC voltage proportional to the magnitude of the respective AC input analog voltage, comparator means responsive to the integrated output voltage of said integrating means to indicate the sign and amplitude of the integrated output voltage of each said integrating means, control logic responsive to the output of said switching logic means corresponding to the said next successive detector output concluding the data integration interval, to initiate a reference integration interval, said control logic responding to the sign indication of said comparator means for supply of a DC reference voltage to each said integrating means of predetermined amplitude and of opposite polarity to the sign indication of the integrated output voltage of the respective integrating means produced thereby in the preceding data integration interval, for integration by said respective integrating means to reduce the respective DC integrated voltage outputs thereof to zero value, the respective intervals of reference voltage integration of said first and second integrating means varying in duration as a function of the respective values of the DC integrated output voltages thereof, first and second counters respectively associated with said first and second integrating means, and said control logiC gating clock pulses of a predetermined repetition rate to each said first and second counters during the respective reference integration intervals thereof and said control logic responding to the zero voltage indication output of said comparator for the respective integrating means to conclude the respective reference integration intervals of the first and second integrating means, to terminate the gating of further clock pulses to the corresponding counters and the supply of the respective DC reference voltages to said corresponding integrating means, each counter producing at the conclusion of the reference integration interval a count output comprising a digital number proportional to the amplitude of the corresponding one of the X-Y and Y-Z analog output voltages for the half-cycle thereof integrated during the preceding data integration interval, said switching logic means closing said first and second clearing switching means at the conclusion of the reference integration interval of the respective first and second integrating means, respectively, to clear the respective integrating means and opening said clearing switching means at the initiation of a successive data integration interval, and wherein, said reference voltages comprise DC compensated reference voltages of equal amplitude and opposite polarity, produced by a compensating circuit in response to the AC reference voltage supplied to the rotor winding of the synchro, comprising: further integrating means, further means operable for the duration of the data integration interval for supply of the AC reference voltage to said further integrating means, and holding means for maintaing the DC integrated voltage output of said further integrating means, developed during the data integration interval, for the duration of the succeeding reference integration interval of said integrating means of said converter, thereby to provide a DC voltage reference output compensated for variations in the AC reference supply voltage, and an inverter receiving the output of said further integrating means for supplying the DC compensated reference voltage of the opposite polarity.