Patent US4965511A successfully refreshed from Google Patents.
US4965511A
Expired / Lapsed
US
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Test circuit for logic ICS
Assignee: Toshiba Corp
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Filing: 1989-06-22
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Granted: 1990-10-23
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Expires: 2009-06-22
Abstract
Abstract A test circuit targeted to test data path blocks such as an arithmetic block to be tested including an arithmetic unit for operating multiple bits as well as including various registers related to the arithmetic unit. The test circuit includes flip-flops for receiving data from a first pin forming a shift register, having the ability of holding data by the control of a test node signal multiplexers for selectively generating control signals for controlling the elements in the data path block to be tested, a second pin connected to the flip-flops and multiplexers to externally provide them with a test mode signal under a test mode, a bus switch connected between a third pin and an internal data bus to control input of test data from the third pin to the arithmetic block and input of an operation result to the third pin via the internal data bus, gates for controlling data input and output with respect to the bus switch, and a timing signal generator for generating timing signals for controlling the gates. At the time of test, the second pin provides the test mode signal. According to this signal, the flip-flops hold test control data, while the multiplexers generate control signals based on the timing signals to test the arithmetic block at high speed.
Inventors
- 👤 Akira Nishimura
- 👤 Yasuyuki Nozuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 00:45
CPC Classifications
G; G11; G11C; G11C29/00; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2226; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
107 words
A test circuit for testing an arithmetic block comprising: (a) holding means for holding a test control signal for achieving a predetermined test in the arithmetic block; (b) selecting means for selectively supplying one of the control signal supplied from an external pin held in said holding means and a normal operation control signal to the arithmetic block according to a test mode signal; (c) switching means for controlling input and output of test data with respect to the arithmetic block; (d) gate means for controlling operation of said switching means; and (e) timing signal generating means for generating a timing signal for controlling said gate means.
Claim 2
Dependent Claim
107 words
A test circuit for testing an arithmetic block comprising: (a) holding means for holding a test control signal for achieving a predetermined test in the arithmetic block; (b) selecting means for selectively supplying one of the control signal supplied from an external pin held in said holding means and a normal operation control signal to the arithmetic block according to a test mode signal; (c) switching means for controlling input and output of test data with respect to the arithmetic block; (d) gate means for controlling operation of said switching means; and (e) timing signal generating means for generating a timing signal for controlling said gate means.
Claim 3
Dependent Claim
69 words
The test circuit as claimed in claim 1, wherein, under a normal operation mode in which said selecting means selects the normal operation control signal and supplies the same to the arithmetic block, said holding means serially transfers and hold the test control signal for achieving the predetermined test, and, under a test operation mode, said holding means supplies the test control signal held therein to said selecting means.
Claim 4
Dependent Claim
244 words
A test circuit comprising: (a) an arithmetic block to be tested including arithmetic means for operating multiple bits as well a including various registers relates to the arithmetic means; (b) a plurality of flip-flops for holding test control data supplied from a first pin, said flip-flops being connected to form a shift register; (c) a plurality of multiplexers for selectively supplying a plurality of test control signals and normal operation control signals to said arithmetic block to be tested to control respectively elements in the arithmetic block; (d) a second pin connected to said flip-flops and multiplexers to provide a test mode signal at the time of test; (e) bus switching means connected between a third pin and an internal data bus to control test data input from the third pin to said arithmetic block via the internal data bus as well as outputting operation results from said arithemtic block to the third pin via the internal data bus; (f) gate means for controlling data input and output with respect to said bus switching means; and (g) timing signal generating means for generating timing signals for controlling said gate means under a test mode, (h) under the test mode, said flip-flops holding the test control data and said multiplexers generating the test control signals according to the test mode signal given by said second pin, while the test data being inputted according to the timing signals thus testing said arithmetic block at high speed.
Claim 5
Dependent Claim
244 words
A test circuit comprising: (a) an arithmetic block to be tested including arithmetic means for operating multiple bits as well a including various registers relates to the arithmetic means; (b) a plurality of flip-flops for holding test control data supplied from a first pin, said flip-flops being connected to form a shift register; (c) a plurality of multiplexers for selectively supplying a plurality of test control signals and normal operation control signals to said arithmetic block to be tested to control respectively elements in the arithmetic block; (d) a second pin connected to said flip-flops and multiplexers to provide a test mode signal at the time of test; (e) bus switching means connected between a third pin and an internal data bus to control test data input from the third pin to said arithmetic block via the internal data bus as well as outputting operation results from said arithemtic block to the third pin via the internal data bus; (f) gate means for controlling data input and output with respect to said bus switching means; and (g) timing signal generating means for generating timing signals for controlling said gate means under a test mode, (h) under the test mode, said flip-flops holding the test control data and said multiplexers generating the test control signals according to the test mode signal given by said second pin, while the test data being inputted according to the timing signals thus testing said arithmetic block at high speed.
Claim 6
Dependent Claim
40 words
The test circuit as claimed in claim 3, further comprising other gate means connected to inputs of predetermined ones of said multiplexers, wherein said timing signal generating means generating means generating other timing signals for controlling the other gate means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |