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US4965215A Expired / Lapsed US ⏱️ 0.0 years remaining

Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip

Assignee: STMicroelectronics SRL
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Filing: 1988-12-21
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Granted: 1990-10-23
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Expires: 2008-12-21
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Abstract

Abstract The device uses the horizontal insulating region and the buried layer as the power transistor base and emitter respectively. An epitaxial growth is interposed between the two diffusions needed to form the aforesaid regions and those needed to create the base and the emitter of the transistor of the integrated control circuit.

Inventors

  • 👤 Raffaele Zambrano
  • 👤 Salvatore Musumeci

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 17:11
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 311 words
A manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip, the phases of which envisage: the epitaxial growth on a semiconductor substrate (11) of a first type of conductivity, of a semiconductor layer (22) which is also of the aforesaid first type of conductivity; the simultaneous formation, by diffusion of doping agent within the surface of the layer (22), of a first semiconductor region (23) and a second semiconductor region (24) of a second type of conductivity, said first region (23) constituting the base region of the power transistor, said second region (24) constituting the horizontal insulating region of the integrated control circuit with respect to the power transistor; the simultaneous formation, by diffusion within the surface of the aforesaid regions (23) and (24), of two regions (25) and (26), respectively, of the first type of conductivity, constituting, respectively, the emitter region of the power transistor and the buried layer of the collector region of the integrated control circuit transistor; the formation, by further subsequent superficial diffusions, of the base (15) and the emitter (16) of the aforesaid transistor of the integrated control circuit; the formation, by simultaneous diffusion, of connecting regions (21) and (19), at the surface (12) of the horizontal insulating region (24) and base region (23) of the power transistor, respectively; the formation, by simultaneous diffusion, of enrichment regions (13) and (14) for the emitter (25) of the power transistor and the buried layer (26) of the integrated control circuit transistor, respectively; characterized by the fact that the formation of the regions (21), (19), (13) and (14) of the base (15) and of the emitter (16) of the transistor of the integrated control circuit is preceded by the epitaxial growth of a semiconductor layer (17) of the first type of conductivity.
Claim 2
Dependent Claim 311 words
A manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip, the phases of which envisage: the epitaxial growth on a semiconductor substrate (11) of a first type of conductivity, of a semiconductor layer (22) which is also of the aforesaid first type of conductivity; the simultaneous formation, by diffusion of doping agent within the surface of the layer (22), of a first semiconductor region (23) and a second semiconductor region (24) of a second type of conductivity, said first region (23) constituting the base region of the power transistor, said second region (24) constituting the horizontal insulating region of the integrated control circuit with respect to the power transistor; the simultaneous formation, by diffusion within the surface of the aforesaid regions (23) and (24), of two regions (25) and (26), respectively, of the first type of conductivity, constituting, respectively, the emitter region of the power transistor and the buried layer of the collector region of the integrated control circuit transistor; the formation, by further subsequent superficial diffusions, of the base (15) and the emitter (16) of the aforesaid transistor of the integrated control circuit; the formation, by simultaneous diffusion, of connecting regions (21) and (19), at the surface (12) of the horizontal insulating region (24) and base region (23) of the power transistor, respectively; the formation, by simultaneous diffusion, of enrichment regions (13) and (14) for the emitter (25) of the power transistor and the buried layer (26) of the integrated control circuit transistor, respectively; characterized by the fact that the formation of the regions (21), (19), (13) and (14) of the base (15) and of the emitter (16) of the transistor of the integrated control circuit is preceded by the epitaxial growth of a semiconductor layer (17) of the first type of conductivity.
Claim 3
Dependent Claim 48 words
A manufacturing process as claimed in claim 1 characterized by the fact that the region (15) of the base of aforesaid integrated control circuit transistor extends from the surface (12) of aforesaid layer (17) as far as the buried layer (26) of the collector region of said transistor.

References Cited (Backward Citations)

US3481801A Cited
US4054899A Cited
US4032372A Cited
US3956035A Cited
US4404048A Cited
US4826780A Cited
US4483738A Cited
US4721684A Cited
US4780430A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-10-22 1994-04-23 1994-10-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-10-22 1998-04-23 1998-10-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-10-22 2002-04-23 2002-10-23 $7700.00 Window Closed / Lapsed

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