Voltage transient protection circuit

Claim 2

A voltage transient protection apparatus for protecting a memory device from a plurality of different undesired control signals provided respectively on a plurality of different control signal paths to said memory device, said apparatus comprising: a plurality of isolation means for isolating said memory device from said control signals in response to a first signal, each of said plurality of isolation means being situated in a different one of said plurality of control signal paths; a primary voltage port for coupling to a primary voltage source of primary voltage; transient detecting means for providing said first signal to said plurality of isolation means when a voltage transient occurs in said primary voltage and, a capacitive secondary voltage source for supplying voltage to said transient detecting means and to said plurality of isolation means for a period of time sufficiently long while said primary voltage is fluctuating during a transient to permit said plurality of isolation means to achieve isolation of said control signals from said memory device, said transient detecting means being coupled to said primary voltage port to sense the primary voltage thereof and being further coupled to said secondary voltage source to receive voltage therefrom to power said transient detecting means.

Claim 3

The voltage transient apparatus of claim 1 including discharge prevention means, coupled between said secondary voltage source and said primary voltage port, to permit said secondary voltage source to receive voltage from said primary voltage port while preventing said secondary voltage source from being discharged through said primary voltage port.

Claim 4

A voltage transient protection apparatus for protecting a memory device from a plurality of different undesired control signals provided on a plurality of respective control signal paths to said memory device, said apparatus comprising: a plurality of tri-state buffers respectively situated in said plurality of control signal paths, each of said tri-state buffers being capable of exhibiting an isolative tri-state mode in response to a first signal, said plurality of tri-state buffers otherwise exhibiting a connective mode; a primary voltage port for coupling said protection apparatus and said memory device to a primary voltage source of primary voltage; transient detecting means for providing said first signal to said plurality of tri-state buffers when a voltage transient occurs in said primary voltage; a capacitive secondary voltage source for supplying voltage to said tri-state buffers and said transient detecting means for a period of time sufficiently long while said primary voltage is fluctuating during a transient to permit said plurality of tri-state buffers to enter said isolative tri-state mode to achieve isolation of said plurality of control signals from said memory device.

Claim 5

A voltage transient protection apparatus for protecting a memory device from a plurality of different undesired control signals provided on a plurality of respective control signal paths to said memory device, said apparatus comprising: a plurality of tri-state buffers respectively situated in said plurality of control signal paths, each of said tri-state buffers being capable of exhibiting an isolative tri-state mode in response to a first signal, said plurality of tri-state buffers otherwise exhibiting a connective mode; a primary voltage port for coupling said protection apparatus and said memory device to a primary voltage source of primary voltage; transient detecting means for providing said first signal to said plurality of tri-state buffers when a voltage transient occurs in said primary voltage; a capacitive secondary voltage source for supplying voltage to said tri-state buffers and said transient detecting means for a period of time sufficiently long while said primary voltage is fluctuating during a transient to permit said plurality of tri-state buffers to enter said isolative tri-state mode to achieve isolation of said plurality of control signals from said memory device.

Claim 6

A voltage transient protection apparatus for protecting a memory device from a plurality of different undesired control signals provided on a plurality of respective control signal paths to said memory device, said apparatus being responsive to a MEMORY DEVICE PRESENT AND STABLE signal which indicates when said memory device is present and stable, said apparatus comprising: a plurality of tri-state buffers situated in said plurality of control signal paths, respectively, each of said tri-state buffers being capable of exhibiting a connective mode in response to a first signal exhibiting a first logic state and an isolative tri-state mode in response to said first signal exhibiting a second logic state; a primary voltage port for coupling said protection apparatus and said memory device to a primary voltage source of primary voltage; transient detecting means for providing a POWER LOW signal to indicate when a negative-going voltage transient occurs in said primary voltage, such transient exhibiting an amplitude less than a predetermined threshold level; logic circuit means, coupled to said plurality of tri-state buffers, for AND'ing said POWER LOW signal with said MEMORY DEVICE PRESENT AND STABLE signal to generate said first signal exhibiting said first logic state to cause said plurality of tri-state buffers to exhibit said connective mode when said POWER LOW signal indicates that a negative going transient in said primary voltage is not presently occurring and said MEMORY DEVICE PRESENT AND STABLE signal indicates that said memory device is present and stable, said logic circuit means otherwise generating said first logic signal exhibiting said second logic state to cause said plurality of tri-state buffers to exhibit said isolative tri-state mode, and a capacitive secondary voltage source for supplying voltage to said transient detecting means, to said logic circuit means, and to said plurality of tri-state buffers, for a period of time sufficiently long while said primary voltage source is collapsing during a negative going transient in said primary voltage to permit said tri-state buffers to enter said isolative tri-state mode to achieve isolation of said plurality of control signals from said memory device.

Claim 7

A voltage transient protection apparatus for protecting a memory device from a plurality of different undesired control signals provided on a plurality of respective control signal paths to said memory device, said apparatus being responsive to a MEMORY DEVICE PRESENT AND STABLE signal which indicates when said memory device is present and stable, said apparatus comprising: a plurality of tri-state buffers situated in said plurality of control signal paths, respectively, each of said tri-state buffers being capable of exhibiting a connective mode in response to a first signal exhibiting a first logic state and an isolative tri-state mode in response to said first signal exhibiting a second logic state; a primary voltage port for coupling said protection apparatus and said memory device to a primary voltage source of primary voltage; transient detecting means for providing a POWER LOW signal to indicate when a negative-going voltage transient occurs in said primary voltage, such transient exhibiting an amplitude less than a predetermined threshold level; logic circuit means, coupled to said plurality of tri-state buffers, for AND'ing said POWER LOW signal with said MEMORY DEVICE PRESENT AND STABLE signal to generate said first signal exhibiting said first logic state to cause said plurality of tri-state buffers to exhibit said connective mode when said POWER LOW signal indicates that a negative going transient in said primary voltage is not presently occurring and said MEMORY DEVICE PRESENT AND STABLE signal indicates that said memory device is present and stable, said logic circuit means otherwise generating said first logic signal exhibiting said second logic state to cause said plurality of tri-state buffers to exhibit said isolative tri-state mode, and a capacitive secondary voltage source for supplying voltage to said transient detecting means, to said logic circuit means, and to said plurality of tri-state buffers, for a period of time sufficiently long while said primary voltage source is collapsing during a negative going transient in said primary voltage to permit said tri-state buffers to enter said isolative tri-state mode to achieve isolation of said plurality of control signals from said memory device.