Gate turn-off thyristor with switching control field effect transistor

Claim 2

A gate turn-off thyristor comprising: (a) a first emitter layer of a first type conductivity; (b) a first base layer of a second type conductivity electrically connected to said first emitter layer and having a surface; (c) a second base layer of the first type conductivity formed in the surface of said first base layer; (d) a second emitter layer of the second type conductivity formed in said second base layer; (e) a gate electrode provided to insulatively cover a portion of said second base layer which is positioned between said second emitter layer and said first base layer, said gate electrode having an elongated planar shape; (f) a control electrode electrically connected to said second base layer, said control electrode comprising, a first electrode portion insulatively provided above said gate electrode and having an elongated planar shape, and second electrode portion for electrically connecting said first electrode portion with said second base layer; (g) an anode electrode formed to be electrically connected to said first emitter layer; and (h) a cathode electrode formed to be electrically connected to said second emitter layer and to insulatively cover said control electrode.

Claim 3

The thyristor according to claim 1, wherein said second electrode portion comprises: a conductive layer extending perpendicularly to said first electrode portion and formed to extend downward from both sides of said gate electrode to be in contact with said second base layer at a certain surface region of said second base layer.

Claim 4

The thyristor according to claim 2, wherein said second emitter layer is substantially uniformly provided in the remaining surface region of said second base layer except for said certain surface region.

Claim 5

The thyristor according to claim 3, further comprising: a spacer electrode formed on said second emitter layer.

Claim 6

The thyristor according to claim 4, further comprising: a spacer electrode sandwiched between said second base layer and said control electrode.

Claim 7

A gate turn-off thyristor comprising: (a) a first emitter layer of a first type conductivity; (b) a first base layer of a second type conductivity electrically connected said first emitter layer and having a surface and first and second directions perpendicular to each other on the surface; (c) two neighboring second base layers of the first type conductivity formed in the surface of said first base layer with a predetermined interval so as to be elongated along said first direction; (d) second emitter layers of the second type conductivity each formed in each of said second base layers; (e) a gate electrode insulatively provided above a portion of said second base layer sandwiched between said second emitter layer and said first base layer and having an elongated planar shape extending along said first direction so as to be substantially self-aligned with said second base layers, said gate electrode defining a field effect transistor structure in a section along said second direction which is perpendicular to an extending direction of said gate electrode; and (f) a control electrode insulatively provided above said gate electrode to have a planar shape elongated along said first direction, said control electrode having, a wiring electrode extending perpendicularly to said control electrode on a plane and formed to extend downward from both sides of said gate electrode to be in contact with certain surface regions of said two neighboring second base layers at certain surface regions of said second base layers, thereby defining a gate turn-off thyristor along said first direction which is parallel to the extending direction of said gate electrode.

Claim 8

A gate turn-off thyristor comprising: (a) a first emitter layer of a first type conductivity; (b) a first base layer of a second type conductivity electrically connected said first emitter layer and having a surface and first and second directions perpendicular to each other on the surface; (c) two neighboring second base layers of the first type conductivity formed in the surface of said first base layer with a predetermined interval so as to be elongated along said first direction; (d) second emitter layers of the second type conductivity each formed in each of said second base layers; (e) a gate electrode insulatively provided above a portion of said second base layer sandwiched between said second emitter layer and said first base layer and having an elongated planar shape extending along said first direction so as to be substantially self-aligned with said second base layers, said gate electrode defining a field effect transistor structure in a section along said second direction which is perpendicular to an extending direction of said gate electrode; and (f) a control electrode insulatively provided above said gate electrode to have a planar shape elongated along said first direction, said control electrode having, a wiring electrode extending perpendicularly to said control electrode on a plane and formed to extend downward from both sides of said gate electrode to be in contact with certain surface regions of said two neighboring second base layers at certain surface regions of said second base layers, thereby defining a gate turn-off thyristor along said first direction which is parallel to the extending direction of said gate electrode.

Claim 9

The thyristor according to claim 6, wherein said control electrode has a mesh-like planar pattern.

Claim 10

The thyristor according to claim 7, further comprising: (g) an anode electrode formed on said first emitter layer; and (h) a cathode electrode formed to be electrically connected to said second emitter layer and to insulatively cover said control electrode.

Claim 11

The thyristor according to claim 8, wherein said second emitter layer is substantially uniformly provided in the remaining surface region of each of said second base layers except for said certain surface region.

Claim 12

The thyristor according to claim 9, wherein said cathode electrode is brought into electrical contact with said second emitter layers at said remaining surface regions.

Claim 13

The thyristor according to claim 10, further comprising: a spacer electrode sandwiched between said second emitter layers and said cathode electrode.

Claim 14

The thyristor according to claim 11, further comprising: spacer electrode having a double-layered structure.

Claim 15

The thyristor according to claim 11, further comprising: a spacer electrode sandwiched between each of said second base layers and said wiring electrode of said control electrode.

Claim 16

A MOS assisted gate turn-off thyristor comprising: (a) a first emitter layer of a first type conductivity; (b) a first base layer of a second type conductivity electrically connected to said first emitter layer and having a surface; (c) second base layers of the first type conductivity elongated in the surface of said first base layer with a predetermined interval; (d) second emitter layers of the second type conductivity formed in said second base layers; (e) gate electrodes insulatively provided above said second base layers and each having an elongated planar shape; and (f) a control electrode having, first conductive layer portions insulatively stacked above said gate electrodes to have elongated planar shapes, and second conductive layer portions, extending perpendicularly to said first conductive layer portions on a plane, for connecting said first conductive layer portions with said second base layers at certain surface regions of said second base layers, said first and second conductive layer portions defining a mesh-like planar pattern.

Claim 17

A MOS assisted gate turn-off thyristor comprising: (a) a first emitter layer of a first type conductivity; (b) a first base layer of a second type conductivity electrically connected to said first emitter layer and having a surface; (c) second base layers of the first type conductivity elongated in the surface of said first base layer with a predetermined interval; (d) second emitter layers of the second type conductivity formed in said second base layers; (e) gate electrodes insulatively provided above said second base layers and each having an elongated planar shape; and (f) a control electrode having, first conductive layer portions insulatively stacked above said gate electrodes to have elongated planar shapes, and second conductive layer portions, extending perpendicularly to said first conductive layer portions on a plane, for connecting said first conductive layer portions with said second base layers at certain surface regions of said second base layers, said first and second conductive layer portions defining a mesh-like planar pattern.

Claim 18

The thyristor according to claim 14, wherein the width of said second conductive layer portions is smaller than the width of said first conductive layer portions.

Claim 19

The thyristor according to claim 14, further comprising: heavily-doped semiconductive layers which have the first conductivity type and which are provided in said certain surface regions, said second conductive layer portions being connected by said heavily-doped semiconductive layers to said second base layers, each of said second emitter layers surrounding the corresponding one of said heavily-doped semiconductive layers on a surface of the corresponding second base layer.

Claim 20

The thyristor according to claim 14, further comprising: heavily-doped semiconductive layers which have the first conductivity type and which are provided in said certain surface regions, said second conductive layer portions being connected by said heavily-doped semiconductive layers to said second base layers, said second base layers being dispersively formed so as to prevent each of said heavily-doped semiconductive layers from being surrounded by the corresponding one of said second emitter layers on a surface of the corresponding second base layer.