US4959835A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1989-01-04
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Granted: 1990-09-25
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Expires: 2009-01-04
Abstract
Abstract A memory management unit is capable of judging that a specific bit has been partially rewritten by checking it against a dummy bit stored in a tag memory which is included in the memory management unit and thus correcting a parity bit. Accordingly, it is possible to accurately execute a parity check operation and it is also possible to improve the throughput of the memory management unit and hence promote lowering in the cost.
Inventors
- 👤 Nobuo Yosida
- 👤 Teruhisa Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:11
CPC Classifications
G; G11; G11C; G11C11/00; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
253 words
A semiconductor memory comprising: a memory array including a plurality of word lines, a plurality of complementary data lines and a plurality of memory cells respectively coupled to the corresponding word lines and the corresponding complementary data lines, wherein to each of said word lines are coupled first memory cells for holding a plurality of bits of data, a second memory cell for holding data representing whether or not said data is valid, a third memory cell for holding parity data concerning the first-mentioned data, and a fourth memory cell for holding data used to make a judgement as to whether or not the data held in said second memory cell has changed; selecting means coupled to said a plurality of word lines, wherein said selecting means selects one word line according to an address signal supplied thereto; check means supplied with data held in the memory cells which are coupled to one word line selected by said selecting means, wherein said check means judges whether or not the pieces of data respectively held in said second and fourth memory cells, which are supplied thereto, are coincident with each other and outputs the result of the judgement; and output means supplied through said check means the data held in said first memory cells and the data held in said second memory cell, wherein said output means, when receiving a coincidence signal from said check means, outputs the data held in said first memory cells and the data held in said second memory cell.
Claim 2
Dependent Claim
253 words
A semiconductor memory comprising: a memory array including a plurality of word lines, a plurality of complementary data lines and a plurality of memory cells respectively coupled to the corresponding word lines and the corresponding complementary data lines, wherein to each of said word lines are coupled first memory cells for holding a plurality of bits of data, a second memory cell for holding data representing whether or not said data is valid, a third memory cell for holding parity data concerning the first-mentioned data, and a fourth memory cell for holding data used to make a judgement as to whether or not the data held in said second memory cell has changed; selecting means coupled to said a plurality of word lines, wherein said selecting means selects one word line according to an address signal supplied thereto; check means supplied with data held in the memory cells which are coupled to one word line selected by said selecting means, wherein said check means judges whether or not the pieces of data respectively held in said second and fourth memory cells, which are supplied thereto, are coincident with each other and outputs the result of the judgement; and output means supplied through said check means the data held in said first memory cells and the data held in said second memory cell, wherein said output means, when receiving a coincidence signal from said check means, outputs the data held in said first memory cells and the data held in said second memory cell.
Claim 3
Dependent Claim
21 words
A semiconductor memory according to claim 1, wherein said check means includes a parity transfer circuit and a parity check circuit.
Claim 4
Dependent Claim
18 words
A semiconductor memory according to claim 2, wherein said parity transfer circuit comprises a plurality of EX-OR circuits.
Claim 5
Dependent Claim
24 words
A semiconductor memory according to claim 2, wherein said parity check circuit comprises a plurality of EX-OR circuits and at least one inverter circuit.
Claim 6
Dependent Claim
18 words
A semiconductor memory according to claim 1, wherein each of said memory cells is a static memory cell.
Claim 7
Dependent Claim
291 words
A microcomputer which is formed on a single semiconductor substrate and which has a CPU, a cache memory means coupled to the CPU and a memory management unit coupled to the CPU and the cache memory means, said memory management unit comprising: a memory array including a plurality of word lines, a plurality of complementary data lines and a plurality of memory cells respectively coupled to the corresponding word lines and the corresponding complementary data lines, wherein to each of said word lines are coupled first memory cells for holding a plurality of bits of data, a second memory cell for holding data representing whether or not said data is valid, a third memory cell for holding parity data concerning the first-mentioned data, and a fourth memory cell for holding data used to make a judgement as to whether or not the data held in said second memory cell has changed; selecting means coupled to said a plurality of word lines, wherein said selecting means selects one word line according to an address signal supplied thereto; check means supplied with data held in the memory cells which are coupled to one word line selected by said selecting means, wherein said check means judges whether or not the pieces of data respectively held in said second and fourth memory cells, which are supplied thereto, are coincident with each other and outputs the result of the judgement; and output means supplied through said check means the data held in said first memory cells and the data held in said second memory cell, wherein said output means, when receiving a coincidence signal from said check means, outputs the data held in said first memory cells and the data held in said second memory cell.
Claim 8
Dependent Claim
291 words
A microcomputer which is formed on a single semiconductor substrate and which has a CPU, a cache memory means coupled to the CPU and a memory management unit coupled to the CPU and the cache memory means, said memory management unit comprising: a memory array including a plurality of word lines, a plurality of complementary data lines and a plurality of memory cells respectively coupled to the corresponding word lines and the corresponding complementary data lines, wherein to each of said word lines are coupled first memory cells for holding a plurality of bits of data, a second memory cell for holding data representing whether or not said data is valid, a third memory cell for holding parity data concerning the first-mentioned data, and a fourth memory cell for holding data used to make a judgement as to whether or not the data held in said second memory cell has changed; selecting means coupled to said a plurality of word lines, wherein said selecting means selects one word line according to an address signal supplied thereto; check means supplied with data held in the memory cells which are coupled to one word line selected by said selecting means, wherein said check means judges whether or not the pieces of data respectively held in said second and fourth memory cells, which are supplied thereto, are coincident with each other and outputs the result of the judgement; and output means supplied through said check means the data held in said first memory cells and the data held in said second memory cell, wherein said output means, when receiving a coincidence signal from said check means, outputs the data held in said first memory cells and the data held in said second memory cell.
Claim 9
Dependent Claim
20 words
A microcomputer according to claim 6, wherein said check means includes a parity transfer circuit and a parity check circuit.
Claim 10
Dependent Claim
17 words
A microcomputer according to claim 7, wherein said parity transfer circuit comprises a plurality of EX-OR circuits.
Claim 11
Dependent Claim
23 words
A microcomputer according to claim 7, wherein said parity check circuit comprises a plurality of EX-OR circuits and at least one inverter circuit.
Claim 12
Dependent Claim
17 words
A microcomputer according to claim 6, wherein each of said memory cells is a static memory cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-24 | 1994-03-26 | 1994-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-24 | 1998-03-26 | 1998-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-24 | 2002-03-26 | 2002-09-25 | $7700.00 | Window Closed / Lapsed |