Error detection using variable field parity checking

Claim 2

A parity checker for a memory storing variable length multibit words having a variable number of parity bits, the checker comprising: a decoder for decoding the variable length words to identify the parity bits contained therein, and to identify selected bits to which said parity bits correspond; and a parity checker coupled to the decoder for checking the parity of the selected bits in said words against the identified parity bits as a function of the variable number of parity bits contained in each word.

Claim 3

The parity checker of claim 1 wherein the decoder identifies both fixed parity bits common to all types of words, and extra parity bits dependent upon the types of words.

Claim 4

The parity checker of claim 1 wherein the decoder identifies the number and location of parity bits as a function of the type of word containing the parity bits.

Claim 5

The parity checker of claim 1 wherein each word comprises a decode field used by the decoder to identify the type of word, and the location of the parity bits.

Claim 6

The parity checker of claim 4 wherein each word comprises a plurality of subfields, and the location of at least one parity bit in selected words is identified by the decoder as a function of the bit in value in one or more such subfields.

Claim 7

The parity checker of claim 1 wherein the words are stored in a plurality of fast access memory modules, the bits of each word being stored on different modules.

Claim 8

The parity checker of claim 6 wherein the bits of words are divided in groups for parity checking purposes, and each module contains at least one bit from one selected group.

Claim 9

The parity checker of claim 7 wherein the bits in each group are spread out over the modules such that a failure of one module will affect the parity of more than one group.

Claim 10

The parity checker of claim 8 wherein the parity bits comprise both fixed and extra parity bits, and wherein the fixed parity bits correspond to the parity of combinations of groups of bits, and selected extra parity bits correspond to the parity of selected groups.

Claim 13

An integrity checker for a memory storing multibit words having a variable number of integrity bits, the checker comprising: word decode means for identifying the integrity bits contained in the multibit words; second means coupled to the word decode means for identifying selected bits corresponding to each integrity bit identified; and integrity checking means coupled to the word decode means and to the seocnd means for checking the integrity of the selected bits in said words against the identified integrity bits as a function of the variable number of integrity bits contained in each word.

Claim 14

An integrity checker for a memory storing multibit words having a variable number of integrity bits, the checker comprising: word decode means for identifying the integrity bits contained in the multibit words; second means coupled to the word decode means for identifying selected bits corresponding to each integrity bit identified; and integrity checking means coupled to the word decode means and to the seocnd means for checking the integrity of the selected bits in said words against the identified integrity bits as a function of the variable number of integrity bits contained in each word.

Claim 15

The integrity checker of claim 11 wherein the integrity bits comprise single bit error correct, double bit error detect error correction code.

Claim 16

The integrity checker of claim 12 wherein the multibit words comprise a plurality of different types, and where the location of bits comprising the error correction code is dependent on the type of word.

Claim 19

A parity checker for a memory storing various classes of multibit words, the parity checker comprising: memory means for storing a multibit word; decode means coupled to the memory means for decoding the word to determine the class of the word; a first plurality of parity generators, each of which is selectively coupled to bit locations of said memory means for generating parity of the bits stored at the locations to which it is selectively coupled; a second plurality of parity checkers, each of which is selectively coupled to single bit locations of the memory means and to at least one of the first plurality of parity generators to receive at least one parity bit therefrom, said secoond plurality of parity checkers generating parity of the bits at the locations to which it is coupled; a plurality of logic gates coupled to the decode means wherein different ones of said logic gates are operative dependent on the class of word decoded by said decode means, said logic gates selecting parity from the second plurality of parity checkers; and parity error checking means coupled to each of the plurality of logic gates for receiving the selected parity from the operative logic gates to generate an error indication if said parity is incorrect.

Claim 20

A parity checker for a memory storing various classes of multibit words, the parity checker comprising: memory means for storing a multibit word; decode means coupled to the memory means for decoding the word to determine the class of the word; a first plurality of parity generators, each of which is selectively coupled to bit locations of said memory means for generating parity of the bits stored at the locations to which it is selectively coupled; a second plurality of parity checkers, each of which is selectively coupled to single bit locations of the memory means and to at least one of the first plurality of parity generators to receive at least one parity bit therefrom, said secoond plurality of parity checkers generating parity of the bits at the locations to which it is coupled; a plurality of logic gates coupled to the decode means wherein different ones of said logic gates are operative dependent on the class of word decoded by said decode means, said logic gates selecting parity from the second plurality of parity checkers; and parity error checking means coupled to each of the plurality of logic gates for receiving the selected parity from the operative logic gates to generate an error indication if said parity is incorrect.