Patent US4959772A successfully refreshed from Google Patents.
US4959772A
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System for monitoring and capturing bus data in a computer
Assignee: Sun Microsystems Inc
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Filing: 1988-03-24
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Granted: 1990-09-25
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Expires: 2008-03-24
Abstract
Abstract A system for troubleshooting or debugging the various modules of a digital computer which are connected to the ports of a common system bus. A control unit transmits serial function and data codes to a serial bus link gate array whose parallel outputs are further processed to generate steering and clock commands. A first set of bus interface multiplexers are connected to each of the lines of the address, data and control fields of the system bus. A second set of multiplexers cause information represented by digital signals on selected ones of the lines in selected ones of the fields to be stored in a plurality of RAMs in response to the steering commands. A trigger logic is provided for selectively starting and stopping different clock signals in response to the clock commands. Information can be stored in the RAMs continuously until the RAMs are full, until a specified smaller amount of information has been stored in the RAMs, or until a specified event occurs, in response to predetermined ones of the function and data codes. The control unit can retrieve and organize the information captured in the RAMs for display to enable a system operator in locating faults in the computer.
Inventors
- 👤 Royston L. Smith
- 👤 Maria V. Rabaza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:42
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0766; G06F11/0772; G06F11/0706; G06F11/0745; G06F11/30; G06F11/34; G06F11/3466; G06F11/349; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
166 words
A system for monitoring and capturing bus data in a digital computer having a CPU, a memory, at least one I/O module, each having a parity generator for generating a parity bit, a system bus for permitting communication between the CPU, memory and I/O module, the system bus including an address filed, a data field and a control field, each field including a plurality of lines for transmitting digital signals representing predetermined information, and a plurality of clock generators for timing the transmission of the digital signals on the lines, a buffer for storing information represented by the digital signals; means for accessing the system bus and storing in the buffer the information represented by the digital signals transmitted on the lines of the fields during pre-selected time intervals; and means for analyzing the information stored in the buffer to locate faults in the computer without disrupting the normal operation thereof; and means for controlling operation of the clock commands of the plurality of clock generators.
Claim 2
Independent Claim
166 words
A system for monitoring and capturing bus data in a digital computer having a CPU, a memory, at least one I/O module, each having a parity generator for generating a parity bit, a system bus for permitting communication between the CPU, memory and I/O module, the system bus including an address filed, a data field and a control field, each field including a plurality of lines for transmitting digital signals representing predetermined information, and a plurality of clock generators for timing the transmission of the digital signals on the lines, a buffer for storing information represented by the digital signals; means for accessing the system bus and storing in the buffer the information represented by the digital signals transmitted on the lines of the fields during pre-selected time intervals; and means for analyzing the information stored in the buffer to locate faults in the computer without disrupting the normal operation thereof; and means for controlling operation of the clock commands of the plurality of clock generators.
Claim 3
Dependent Claim
64 words
A system as recited in claim 1, wherein comprises: means for checking the parity of the predetermined digital codes accessed from the system bus to determine the existence of a parity error; and means for generating a parity error signal in response to each parity error determined by the parity checking means; and means for transmitting the parity error signal on the system bus.
Claim 4
Dependent Claim
37 words
A system as recited in claim 2, wherein the parity error signal generating means is generates the parity error signal on a clock cycle immediately following the determination of a parity error by the parity checking means.
Claim 5
Dependent Claim
67 words
A system as recited in claim 1, wherein the computer further has a control unit that transmits a plurality of function and data codes in serial form on a serial bus, and the accessing and storing means includes a serial bus link gate array connected to the control unit via the serial bus for receiving the serial function and data codes and converting them into parallel form.
Claim 6
Dependent Claim
60 words
A system as recited in claim 4, wherein the accessing and storing means further includes a decode logic circuit for receiving the parallel function and data codes from the serial bus link gate array and converting them into a plurality of steering commands that determine which of the selected fields and lines of the system bus are to be accessed.
Claim 7
Dependent Claim
38 words
A system as recited in claim 5, wherein the accessing and storing means further includes a plurality of bus interface multiplexers for transferring digital signals from the system bus to the buffer in response to the steering commands.
Claim 8
Dependent Claim
50 words
A system as recited in claim 6, wherein the means for analyzing the information stored in the buffer to be analyzed includes a plurality of output multiplexers for accessing information stored in the buffer and transmitting it to the serial bus link gate array in parallel form under preset conditions.
Claim 9
Dependent Claim
46 words
A system as recited in claim 1, and further comprising means connected to the accessing and storing means for storing information in the buffer continuously until the buffer is full, until a specified smaller amount of information has been stored, or until a specified event occurs.
Claim 10
Dependent Claim
40 words
A system as recited in claim 1, and further comprising means for diagnosing faults in the bus data monitoring and capturing system which are separate and apart from faults in the computer without disrupting the normal operation of the computer.
Claim 11
Independent Claim
280 words
A system for monitoring and capturing bus data in a digital computer having a CPU, a memory, at least one I/O module, each having a parity generator for generating a parity bit, system bus for permitting communication between the CPU, memory and I/O module, the system bus including an address field, a data field and a control field, each field including a plurality of lines for transmitting digital signals representing predetermined information, and a plurality of clock generators for timing the transmission of the digital signals on the lines, comprising: a control unit that transmits a plurality of function and data codes in serial form on a serial bus; first interface means connected to the control unit via the serial bus for receiving the function and data codes and converting them into parallel form; means for receiving the parallel function and data codes from the first interface means and converting them into a plurality of steering commands that select the lines of the fields and a plurality of clock commands that start or stop one or more of the clocks; and a buffer for storing information represented by the digital signals; second interface means for transferring digital signals from the system bus to the buffer in response to the steering commands; trigger means connected to the buffer for starting or stopping the transfer of digital signals from the system bus to the buffer in response to the clock commands; and output means for connecting the buffer to the first interface means so that the information stored in the buffer may be accessed by the control unit in order to locate faults in the computer without disrupting the normal operation thereof.
Claim 12
Independent Claim
280 words
A system for monitoring and capturing bus data in a digital computer having a CPU, a memory, at least one I/O module, each having a parity generator for generating a parity bit, system bus for permitting communication between the CPU, memory and I/O module, the system bus including an address field, a data field and a control field, each field including a plurality of lines for transmitting digital signals representing predetermined information, and a plurality of clock generators for timing the transmission of the digital signals on the lines, comprising: a control unit that transmits a plurality of function and data codes in serial form on a serial bus; first interface means connected to the control unit via the serial bus for receiving the function and data codes and converting them into parallel form; means for receiving the parallel function and data codes from the first interface means and converting them into a plurality of steering commands that select the lines of the fields and a plurality of clock commands that start or stop one or more of the clocks; and a buffer for storing information represented by the digital signals; second interface means for transferring digital signals from the system bus to the buffer in response to the steering commands; trigger means connected to the buffer for starting or stopping the transfer of digital signals from the system bus to the buffer in response to the clock commands; and output means for connecting the buffer to the first interface means so that the information stored in the buffer may be accessed by the control unit in order to locate faults in the computer without disrupting the normal operation thereof.
Claim 13
Dependent Claim
19 words
A system as recited in claim 10, wherein the first interface means includes a serial bus link gate array.
Claim 14
Dependent Claim
85 words
A system as recited in claim 10, wherein the second interface means includes a plurality of interface multiplexers connected to the lines of the address, data and control fields of the system bus for transferring the digital signals transmitted on each of the lines and a plurality of snapshot multiplexers connected to the interface multiplexers for selecting predetermined ones of the lines for causing the information represented by the digital signals transmitted thereon to be stored in the buffer in response to the steering commands.
Claim 15
Dependent Claim
30 words
A system as recited in claim 10, wherein the output means includes a plurality of multiplexers for transferring information from the buffer to the first interface means under preset conditions.
Claim 16
Dependent Claim
67 words
A system as recited in claim 10, wherein the system further comprises: means for checking the parity of the predetermined digital codes accessed from the system bus to determine the existence of a parity error; and means for generating a parity error signal in response to each parity error determined by the parity checking means; and means for transmitting the parity error signal on the system bus.
Claim 17
Dependent Claim
36 words
A system as recited in claim 14, wherein the parity error signal generating means generates the parity error signal on a clock cycle immediately following the determination of a parity error by the parity checking means.
Claim 18
Dependent Claim
46 words
A system as recited in claim 10, and further comprising means connected to the accessing and storing means for storing information in the buffer continuously until the buffer is full, until a specified smaller amount of information has been stored, or until a specified event occurs.
Claim 19
Dependent Claim
40 words
A system as recited in claim 10, and further comprising means for diagnosing faults in the bus data monitoring and capturing system which are separate and apart from faults in the computer without disrupting the normal operation of the computer.
Claim 20
Dependent Claim
36 words
A system as recited in claim 10, wherein the trigger means includes means for setting and clearing a predetermined break point in the transfer of digital signals from the system bus by the second interface means.
Claim 21
Independent Claim
341 words
A system for monitoring and capturing bus data in a digital computer having a CPU, a memory, at least one I/O module, each having a parity generator for generating a parity bit, a system bus for permitting communication between the CPU, memory and I/O module, the system bus including an address field, a data field and a control field, each field including a plurality of lines for transmitting digital signals representing predetermined information, and a plurality of clock generators for timing the transmission of the digital signals on the lines, comprising: a control unit that transmits a plurality of function and data codes in serial form on a serial bus; a serial bus link gate array connected to the control unit via the serial bus for receiving the function and data codes and converting them into parallel form; means for receiving the parallel function and data codes from the serial bus link gate array converting them into a plurality of steering commands that select the lines of the fields and a plurality of clock commands that start or stop one or more of the clocks; a plurality of random access memories (RAMs) for storing information represented by the digital signals; second interface means for transferring digital signals from the system bus to the RAMs in response to the steering commands, including a first set of multiplexers connected to each of the lines of each of the bus fields, and a second set of multiplexers for selectively transferring the signals on the selected lines of the selected fields in accordance with the steering commands; trigger means connected to the buffer for starting or stopping the transfer of digital signals from the system bus to the RAMs in response to the clock commands; and output means for connecting the RAMs to the first interface means so that the information stored in the RAMs may be accessed by the control unit in order to locate faults in the computer without disrupting the normal operation thereof, the output means including a third set of multiplexers.
Claim 22
Independent Claim
341 words
A system for monitoring and capturing bus data in a digital computer having a CPU, a memory, at least one I/O module, each having a parity generator for generating a parity bit, a system bus for permitting communication between the CPU, memory and I/O module, the system bus including an address field, a data field and a control field, each field including a plurality of lines for transmitting digital signals representing predetermined information, and a plurality of clock generators for timing the transmission of the digital signals on the lines, comprising: a control unit that transmits a plurality of function and data codes in serial form on a serial bus; a serial bus link gate array connected to the control unit via the serial bus for receiving the function and data codes and converting them into parallel form; means for receiving the parallel function and data codes from the serial bus link gate array converting them into a plurality of steering commands that select the lines of the fields and a plurality of clock commands that start or stop one or more of the clocks; a plurality of random access memories (RAMs) for storing information represented by the digital signals; second interface means for transferring digital signals from the system bus to the RAMs in response to the steering commands, including a first set of multiplexers connected to each of the lines of each of the bus fields, and a second set of multiplexers for selectively transferring the signals on the selected lines of the selected fields in accordance with the steering commands; trigger means connected to the buffer for starting or stopping the transfer of digital signals from the system bus to the RAMs in response to the clock commands; and output means for connecting the RAMs to the first interface means so that the information stored in the RAMs may be accessed by the control unit in order to locate faults in the computer without disrupting the normal operation thereof, the output means including a third set of multiplexers.
Claim 23
Dependent Claim
67 words
A system as recited in claim 19, wherein the system further comprises: means for checking the parity of the predetermined digital codes accessed from the system bus to determine the existence of a parity error; and means for generating a parity error signal in response to each parity error determined by the parity checking means; and means for transmitting the parity error signal on the system bus.
Claim 24
Dependent Claim
37 words
A system as recited in claim 20, wherein the parity error signal generating means is generates the parity error signal on a clock cycle immediately following the determination of a parity error by the parity checking means.
Claim 25
Dependent Claim
62 words
A system as recited in claim 19, further comprising means connected to the second interface means and the trigger means for storing information in the RAMs continuously until the RAMs are full, until a specified smaller amount of information has been stored in the RAMs, or until a specified event occurs, in response to predetermined ones of the function and data codes.
Claim 26
Dependent Claim
39 words
A system as recited in claim 19, further comprising means for diagnosing faults in the bus data monitoring and capturing system which are separate and apart from faults in the computer without disrupting the normal operation of the computer.
Claim 27
Dependent Claim
36 words
A system as recited in claim 19, wherein the trigger means includes means for setting and clearing a predetermined break point in the transfer of digital signals from the system bus by the second interface means.
References Cited (Backward Citations)
US3999053A
Cited
US4166290A
Cited
US4308615A
Cited
US4392208A
Cited
US4459656A
Cited
US4636941A
Cited
US4639917A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-24 | 1994-03-26 | 1994-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-24 | 1998-03-26 | 1998-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-24 | 2002-03-26 | 2002-09-25 | $7700.00 | Window Closed / Lapsed |