Patent US4959623A successfully refreshed from Google Patents.
US4959623A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low impedance buffer circuit
Assignee: Nokia Bell Labs
•
Filing: 1989-07-19
•
Granted: 1990-09-25
•
Expires: 2009-07-19
Abstract
Abstract A low impedance class AB buffer stage in complementary transistor technology has its quiescient current stabilized and its operation thereby made more reliable by means of suitable error op-amps that are supplied with transistor feedback loops which are connected to the stage's output terminal through resistors. In addition, for full rail-to-rail output voltage capability, transistor switching devices are added to turn off current through either of the resistors when the output voltage approaches the voltage of either power rail, and also a pair of serially rail-to-rail connected transistor is connected in parallel with the feedback loops.
Inventors
- 👤 John M. Khoury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:17
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/30; H03F3/3001; H03F2203/00; H03F2203/30; H03F2203/30057; H03F2203/30078; H03F2203/30096; H03F2203/30111; H03F2203/30129
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
214 words
Amplifier circuitry including a buffer stage which comprises (a) first and second operational amplifiers each having an output terminal and a first and a second input terminal; (b) first and second resistance means; (c) first and second transistor devices respectively having first and second relatively high current carrying controlled paths and respectively having first and second relatively low current carrying control terminals; (d) first and second power rails; (e) first connection means for connecting, from the first power rail to the second power rail, serially the first high current path of the first transistor device, the first resistance means, the second resistance means, and the second high current path of the second transistor device; (f) second connection means for connecting a first node located between the first transistor device and the first resistance means to the second input terminal of the first operational amplifier; (g) third connection means for connecting a second node located between the second transistor device and the second resistance means to the second input terminal of the second operational amplifier; and (h) fourth and fifth connection means for connecting respectively the output terminal of the first operational amplifier and of the second operational amplifier to the control terminal of the first transistor device and of the second transistor device, respectively.
Claim 2
Dependent Claim
214 words
Amplifier circuitry including a buffer stage which comprises (a) first and second operational amplifiers each having an output terminal and a first and a second input terminal; (b) first and second resistance means; (c) first and second transistor devices respectively having first and second relatively high current carrying controlled paths and respectively having first and second relatively low current carrying control terminals; (d) first and second power rails; (e) first connection means for connecting, from the first power rail to the second power rail, serially the first high current path of the first transistor device, the first resistance means, the second resistance means, and the second high current path of the second transistor device; (f) second connection means for connecting a first node located between the first transistor device and the first resistance means to the second input terminal of the first operational amplifier; (g) third connection means for connecting a second node located between the second transistor device and the second resistance means to the second input terminal of the second operational amplifier; and (h) fourth and fifth connection means for connecting respectively the output terminal of the first operational amplifier and of the second operational amplifier to the control terminal of the first transistor device and of the second transistor device, respectively.
Claim 3
Dependent Claim
31 words
The circuitry of claim 1 which further comprises fourth connection means for connecting a node located between the first and second resistance means to an output terminal of the buffer stage.
Claim 4
Dependent Claim
12 words
A semiconductor integrated circuit including the amplifier circuitry recited in claim 1.
Claim 5
Dependent Claim
74 words
Amplifier circuitry in accordance with claim 1 which further comprises: third and fourth transistor devices having respectively third and fourth relatively low current carrying control terminals that are coupled respectively to the first and second control terminals of the first and second transistor devices, respectively, the third and fourth transistor devices having respectively third and fourth relatively high current paths that are connected serially from the first power rail to the second power rail.
Claim 6
Dependent Claim
48 words
A semiconductor integrated circuit in accordance with claim 4 in which the channel width to length ratio of the third transistor device and of the fourth transistor device is at least five times greater than that of the first transistor device and of the second transistor device, respectively.
Claim 7
Dependent Claim
45 words
A circuit in accordance with claim 4 further comprising fifth and sixth transistor devices whose high current paths are respectively connected in series with that of the first and second transistor devices, and whose control terminals are respectively connected to the first and second nodes.
Claim 8
Dependent Claim
11 words
A semiconductor integrated circuit including the circuitry recited in claim 6.
Claim 9
Dependent Claim
11 words
In a semiconductor integrated circuit, the circuitry recited in claim 4.
Claim 10
Dependent Claim
151 words
Amplifier circuitry in accordance with claim 1 further including a voltage gain stage having first and second output terminals that are connected to the first input terminal of the first and second operational amplifiers, respectively, the voltage gain stage comprising (a) current source means for supplying a constant current; (b) third resistor means having first and second terminals; (c) a seventh transistor device having a control terminal that is connected to a circuitry input terminal for receiving an input signal voltage, the seventh transistor device having a high current path suitable for carrying the constant current; (d) connecting means for connecting, from the first rail to the second rail, serially the current source means, the third resistor means, and the seventh transistor device; and (e) connecting means for connecting the first and second terminals of the resistance means to the first input terminal of the first and second operational amplifiers, respectively.
Claim 11
Dependent Claim
11 words
In a semiconductor integrated circuit, the amplifier circuitry of claim 9.
Claim 12
Dependent Claim
119 words
Amplifier circuitry according to claim 4 further including: (a) current source means for supplying a constant current; (b) third resistance means having first and second terminals; (c) a seventh transistor device having a control terminal that is connected to a circuitry input terminal for receiving an input signal voltage, the seventh transistor having a high current path suitable for carrying the constant current; (d) connecting means for connecting, from the first rail to the second rail, serially the current source means, the third resistance means, and the seventh transistor device; and (e) connecting means for connecting the first and second terminals of the third resistance means to the first input terminal of the first and second operational amplifiers, respectively.
Claim 13
Dependent Claim
11 words
In a semiconductor integrated circuit, the amplifier circuitry of claim 11.
Claim 14
Dependent Claim
37 words
The amplifier circuitry of claim 9 in which the constant current multiplied by the resistance of the third resistance means is at least about 5 times the input offset voltage of the first and second operational amplifiers.
References Cited (Backward Citations)
US4306199A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-24 | 1994-03-26 | 1994-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-24 | 1998-03-26 | 1998-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-24 | 2002-03-26 | 2002-09-25 | $7700.00 | Window Closed / Lapsed |