Patent US4958276A successfully refreshed from Google Patents.
US4958276A
Expired / Lapsed
US
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Single chip processor
Assignee: Hitachi Ltd
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Filing: 1987-12-04
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Granted: 1990-09-18
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Expires: 2007-12-04
Abstract
Abstract In a single chip processor which can be provided with an extended program memory, a high-speed access can be executed without being restricted by the access time for the external program memory when an internal program memory is employed, by varying the effective instruction cycle, and thus a high-speed processing performance for a single chip processor of a stored program type can be attained.
Inventors
- 👤 Atsushi Kiuchi
- 👤 Kenji Kaneko
- 👤 Jun Ishida
- 👤 Tetsuya Nakagawa
- 👤 Yoshimune Hagiwara
- 👤 Takashi Akazawa
- 👤 Tomoru Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7842
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
120 words
A single chip processor to be coupled to an external program memory which stores instructions, comprising: (a) a processing circuit; (b) an internal program memory for storing instructions; (c) a program counter for generating addresses for an access to said external program memory and said internal program memory in response to a signal from said processing circuit; (d) detecting means for determining whether an address generated by said program counter is an address for reading an instruction from said external program memory or an address for reading an instruction from said internal program memory; and (e) means for varying the instruction cycle time of said single chip processor in accordance with the result of the determination by said detecting means.
Claim 2
Dependent Claim
120 words
A single chip processor to be coupled to an external program memory which stores instructions, comprising: (a) a processing circuit; (b) an internal program memory for storing instructions; (c) a program counter for generating addresses for an access to said external program memory and said internal program memory in response to a signal from said processing circuit; (d) detecting means for determining whether an address generated by said program counter is an address for reading an instruction from said external program memory or an address for reading an instruction from said internal program memory; and (e) means for varying the instruction cycle time of said single chip processor in accordance with the result of the determination by said detecting means.
Claim 3
Dependent Claim
46 words
A single chip processor according to claim 1, wherein said means for varying the instruction cycle time of the single chip processor is a clock signal generator having means for changing the output frequency thereof in accordance with the result of determination by said detecting means.
Claim 4
Dependent Claim
70 words
A single chip processor according to claim 1, wherein said means for varying the instruction cycle time of the single chip processor comprises means for changing the period of address generation by said program counter in accordance with the result of determination by said detecting means, and means for holding said processing circuit in a state of no operation during a prescribed time in one period of said address output.
Claim 5
Dependent Claim
42 words
A single chip processor according to claim 1, further comprising switching means for switching over selectively an output of said external program memory and an output of said internal program memory in accordance with the result of determination by said detecting means.
Claim 6
Dependent Claim
34 words
A single chip processor according to claim 1, wherein said external program memory is a memory of a low-speed operation type while said internal program memory is a memory of a high-speed operation type.
Claim 7
Dependent Claim
123 words
A single chip processor to be coupled to an external program memory which stores instructions, comprising: (a) a processing circuit; (b) an internal program memory for storing instructions; (c) a program counter for generating addresses for an access to said external program memory and said internal program memory in response to a signal from said processing circuit; (d) detecting means for determining whether an address generated by said program counter is an address for reading an instruction from said external program memory or an address for reading an instruction from said internal program memory; and (e) means for controlling the timing of start of execution of an instruction by said processing circuit in accordance with the result of determination by said detecting means.
Claim 8
Dependent Claim
123 words
A single chip processor to be coupled to an external program memory which stores instructions, comprising: (a) a processing circuit; (b) an internal program memory for storing instructions; (c) a program counter for generating addresses for an access to said external program memory and said internal program memory in response to a signal from said processing circuit; (d) detecting means for determining whether an address generated by said program counter is an address for reading an instruction from said external program memory or an address for reading an instruction from said internal program memory; and (e) means for controlling the timing of start of execution of an instruction by said processing circuit in accordance with the result of determination by said detecting means.
Claim 9
Dependent Claim
49 words
A single chip processor according to claim 6, wherein said means for controlling the timing of start of execution of an instruction by said processing circuit is a clock generator having means for changing the output frequency thereof in accordance with the result of determination by said detecting means.
Claim 10
Dependent Claim
63 words
A single chip processor according to claim 6, wherein said means for controlling the timing of start of execution of an instruction by the processing circuit comprises means for changing the period of address generating by said detecting means, and means for holding said processing circuit in a state of no operation during a prescribed time in one period of said address output.
Claim 11
Dependent Claim
42 words
A single chip processor according to claim 6 further comprising switching means for switching over selectively an output of said external program memory and an output of said internal program memory in accordance with the result of determination by said detecting means.
Claim 12
Dependent Claim
34 words
A single chip processor according to claim 6, wherein said external program memory is a memory of a low-speed operation type, while said internal program memory is a memory of a high-speed operation type.
References Cited (Backward Citations)
US4171536A
Cited
US4651275A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-17 | 1994-03-19 | 1994-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-17 | 1998-03-19 | 1998-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-17 | 2002-03-19 | 2002-09-18 | $7700.00 | Window Closed / Lapsed |