Non-current hogging dual phase splitter TTL circuit

Claim 2

A TTL circuit having dual transistor elements with respective base and emitter nodes coupled in current mirror configuration, said dual transistor elements having separately coupled collector nodes coupled respectively to separate collector current sources, comprising: a low impedance current sourcing active transistor element operatively coupled in emitter follower configuration in parallel with one of the collector current sources at a collector node of one of the dual transistor elements, said emitter follower configuration active transistor element supplying compensating collector current for mirroring of the currents at the respective emitter nodes of the dual transistor elements substantially without base drive current hogging between the dual transistor elements.

Claim 3

A TTL circuit comprising: dual transistor elements including a primary reference transistor element and a secondary transistor element, said reference and secondary transistor elements having base nodes and emitter nodes coupled in current mirror configuration; said reference transistor element having a collector node coupled to a substantially constant collector load and collector current thereby providing a reference emitter current density; said secondary transistor element having a collector node coupled to a variable collector load generating variable collector current; and a low impedance current sourcing active transistor element operatively coupled in emitter follower configuration at the collector node of the secondary transistor element in parallel with the variable collector load, said emitter follower configuration active transistor element supplying compensating collector current for mirroring of the currents at the respective emitter nodes of the dual transistor elements substantially without base drive current hogging between the dual transistor elements.

Claim 4

A TTL circuit comprising: dual transistor elements including a primary reference transistor element and a secondary transistor element, said reference and secondary transistor elements having base nodes and emitter nodes coupled in current mirror configuration; said reference transistor element having a collector node coupled to a substantially constant collector load and collector current thereby providing a reference emitter current density; said secondary transistor element having a collector node coupled to a variable collector load generating variable collector current; and a low impedance current sourcing active transistor element operatively coupled in emitter follower configuration at the collector node of the secondary transistor element in parallel with the variable collector load, said emitter follower configuration active transistor element supplying compensating collector current for mirroring of the currents at the respective emitter nodes of the dual transistor elements substantially without base drive current hogging between the dual transistor elements.

Claim 5

The TTL circuit of claim 2 wherein the variable collector load at the collector node of the secondary transistor element comprises a supplemental circuit which operates without direct connection to the collector node of the reference transistor element.

Claim 6

A TTL circuit having an output for delivering signals of high and low potential, a pulldown transistor element for sinking current from the output to ground, a pullup transistor element for sourcing current to the output from a power supply, and dual phase splitter transistor elements operatively coupled with respective base nodes and emitter nodes in current mirror configuration, a first one of said phase splitter transistor elements being coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements, said first phase splitter transistor element having a collector node coupled to the pullup transistor element, and a second one of the phase splitter transistor elements having a collector node operatively coupled in a supplemental circuit without direct connection to the collector node of the first phase splitter transistor element and the pullup transistor element, the improvement comprising: a low impedance current sourcing active transistor element operatively coupled in emitter follower configuration at the collector node of the second dual phase splitter transistor element in parallel with the supplemental circuit, said emitter follower configuration active transistor element supplying compensating collector current for mirroring of the currents at the respective emitter nodes of the dual phase splitter transistor elements substantially without base drive current hogging between the dual phase splitter transistor elements.

Claim 7

A TTL circuit having an output for delivering signals of high and low potential, a pulldown transistor element for sinking current from the output to ground, a pullup transistor element for sourcing current to the output from a power supply, and dual phase splitter transistor elements operatively coupled with respective base nodes and emitter nodes in current mirror configuration, a first one of said phase splitter transistor elements being coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements, said first phase splitter transistor element having a collector node coupled to the pullup transistor element, and a second one of the phase splitter transistor elements having a collector node operatively coupled in a supplemental circuit without direct connection to the collector node of the first phase splitter transistor element and the pullup transistor element, the improvement comprising: a low impedance current sourcing active transistor element operatively coupled in emitter follower configuration at the collector node of the second dual phase splitter transistor element in parallel with the supplemental circuit, said emitter follower configuration active transistor element supplying compensating collector current for mirroring of the currents at the respective emitter nodes of the dual phase splitter transistor elements substantially without base drive current hogging between the dual phase splitter transistor elements.

Claim 8

The TTL circuit of claim 4 comprising an input transistor element having an emitter node operatively coupled to the base nodes of the dual phase splitter transistor elements and wherein the base node of the current sourcing active transistor element is coupled to the collector node of the input transistor element for base drive.

Claim 9

A TTL circuit having an output for delivering data signals of high and low potential, a pulldown transistor element for sinking current from the output to ground, a pullup transistor element for sourcing current to the output from a power supply, and dual phase splitter transistor elements operatively coupled with respective base nodes and emitter nodes in current mirror configuration, said dual phase splitter transistors including an output phase splitter transistor element operatively coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements, said output phase splitter transistor element having a collector node coupled to the pullup transistor element, and at least one secondary phase splitter transistor element having a supplemental circuit coupled to the collector node of the secondary phase splitter transistor element without direct connection to the collector node of the output phase splitter transistor element and the pullup transistor element, the improvement for reducing any current hogging that might occur at the base nodes of the dual phase splitter transistor elements comprising: a low impedance current sourcing active transistor element operatively coupled in substantial emitter follower configuration at the collector node of the secondary phase splitter transistor element in parallel with the supplemental circuit, said emitter follower configuration active transistor element supplying compensating collector current for mirroring of the currents at the respective emitter nodes of the dual phase splitter transistor elements substantially without base drive current hogging between the dual phase splitter transistor elements.

Claim 10

A TTL circuit having an output for delivering data signals of high and low potential, a pulldown transistor element for sinking current from the output to ground, a pullup transistor element for sourcing current to the output from a power supply, and dual phase splitter transistor elements operatively coupled with respective base nodes and emitter nodes in current mirror configuration, said dual phase splitter transistors including an output phase splitter transistor element operatively coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements, said output phase splitter transistor element having a collector node coupled to the pullup transistor element, and at least one secondary phase splitter transistor element having a supplemental circuit coupled to the collector node of the secondary phase splitter transistor element without direct connection to the collector node of the output phase splitter transistor element and the pullup transistor element, the improvement for reducing any current hogging that might occur at the base nodes of the dual phase splitter transistor elements comprising: a low impedance current sourcing active transistor element operatively coupled in substantial emitter follower configuration at the collector node of the secondary phase splitter transistor element in parallel with the supplemental circuit, said emitter follower configuration active transistor element supplying compensating collector current for mirroring of the currents at the respective emitter nodes of the dual phase splitter transistor elements substantially without base drive current hogging between the dual phase splitter transistor elements.

Claim 11

The TTL circuit of claim 6 wherein the TTL circuit comprises an input transistor element operatively coupled to the dual phase splitter transistor elements for receiving and applying input signals of high and low potential, wherein the base node of the current sourcing active transistor element is coupled to the collector node of the input transistor element and wherein the respective base nodes of the dual phase splitter transistor elements are coupled in parallel to the emitter node of the input transistor element.

Claim 12

The TTL circuit of claim 6 wherein the emitter area of the secondary phase splitter transistor element is slightly larger than the emitter area of the output phase splitter transistor element.

Claim 13

The TTL circuit of claim 6 further comprising an AC Miller killer circuit coupled to the base nodes of the dual phase splitter transistor elements to accelerate turn off of the dual phase splitter transistor elements during transition from low to high potential at the output.

Claim 14

The TTL circuit of claim 9 wherein the AC Miler killer circuit comprises an active discharge transistor element having the base node of the active discharge transistor element coupled to the emitter node of the emitter follower configuration current sourcing active transistor element.

Claim 15

The TTL circuit of claim 6 wherein the collector node of the secondary phase splitter transistor element is coupled in a supplemental circuit which delivers variable collector current to the secondary phase splitter transistor element.

Claim 16

The TTL circuit of claim 11 wherein the supplemental circuit comprises a cross feedback circuit of a JK flip flop circuit.

Claim 17

The TTL circuit of claim 6 further comprising a bias circuit coupled to the emitter follower configuration current sourcing active transistor element to maintain the current sourcing active transistor element at least in a slightly conducting state.

Claim 18

A TTL JK flip flop circuit having first and second master input circuits for receiving input signals of high and low potential, first and second slave output buffer circuits having respective inputs operatively coupled to the respective first and second input circuits for controlling the state of the output buffer circuits according to input signals, said first and second output buffer circuits each comprising an output for delivering output signals of high and low potential, pullup transistor element for sourcing current to the output from a power supply, pulldown transistor element for sinking current from the output to low potential, phase splitter transistor element coupled to the input and to the pullup and pulldown transistor elements for controlling the conducting states of the respective pullup and pulldown transistor elements, said flip flop circuit further comprising first and second cross feedback circuits each including a cross feedback transistor element operatively coupled between one of the input circuits and the other of the output buffer circuits, the improvement comprising: each output buffer circuit comprising dual phase splitter transistor elements including an output phase splitter transistor element operatively coupled to the pullup and pulldown transistor elements of the output buffer circuit for controlling the respective states of the pullup and pulldown transistor elements, and at least one secondary phase splitter transistor element operatively coupled in current mirror configuration with the output phase splitter transistor element, said secondary phase splitter transistor element being coupled at its collector node to the respective cross feedback circuit without direct connection to the pullup transistor element and output, thereby isolating the cross feedback transistor element in the cross feedback circuit from the pullup transistor element and output and avoiding feedback transistor breakdown when the output is at high potential.

Claim 19

A TTL JK flip flop circuit having first and second master input circuits for receiving input signals of high and low potential, first and second slave output buffer circuits having respective inputs operatively coupled to the respective first and second input circuits for controlling the state of the output buffer circuits according to input signals, said first and second output buffer circuits each comprising an output for delivering output signals of high and low potential, pullup transistor element for sourcing current to the output from a power supply, pulldown transistor element for sinking current from the output to low potential, phase splitter transistor element coupled to the input and to the pullup and pulldown transistor elements for controlling the conducting states of the respective pullup and pulldown transistor elements, said flip flop circuit further comprising first and second cross feedback circuits each including a cross feedback transistor element operatively coupled between one of the input circuits and the other of the output buffer circuits, the improvement comprising: each output buffer circuit comprising dual phase splitter transistor elements including an output phase splitter transistor element operatively coupled to the pullup and pulldown transistor elements of the output buffer circuit for controlling the respective states of the pullup and pulldown transistor elements, and at least one secondary phase splitter transistor element operatively coupled in current mirror configuration with the output phase splitter transistor element, said secondary phase splitter transistor element being coupled at its collector node to the respective cross feedback circuit without direct connection to the pullup transistor element and output, thereby isolating the cross feedback transistor element in the cross feedback circuit from the pullup transistor element and output and avoiding feedback transistor breakdown when the output is at high potential.

Claim 20

The TTL JK flip flop circuit of claim 14 further comprising a current sourcing transistor element coupled in substantial emitter follower configuration at the collector node of the secondary phase splitter transistor element for supplying mirroring current through the emitter of the secondary phase splitter transistor element.

Claim 21

The TTL JK flip flop circuit of claim 15 wherein the cross feedback circuit comprises a variable collector load at the collector of the secondary phase splitter transistor and wherein the current sourcing transistor is operatively coupled in parallel with the cross feedback circuit at the collector node of the phase splitter transistor element to provide a variable current which varies inversely with the cross feedback circuit collector load current.

Claim 22

The TTL JK flip flop circuit of claim 15 wherein the output buffer circuit comprises an input transistor element having an emitter node operatively coupled to the base nodes of the dual phase splitter transistor elements and wherein the base node of the current sourcing transistor element is coupled to the collector node of the input transistor element.

Claim 23

The TTL JK flip flop circuit of claim 15 wherein the base node of the current sourcing transistor element is coupled to a current source node of the output buffer circuit out of phase with the input signal.

Claim 24

The TTL JK flip flop circuit of claim 15 further comprising a supplemental A.C Miller killer circuit coupled at the base nodes of the dual phase splitter transistor elements for accelerating turn off of the dual phase splitter transistor elements during transition from low to high potential at the output.

Claim 25

The TTL JK flip flop circuit of claim 15 wherein the output buffer circuit further comprises a biasing circuit operatively coupled between the emitter node of the current sourcing transistor and ground to maintain the current sourcing transistor at least in a slightly conducting state.

Claim 26

A TTL JK flip flop circuit having J and K input circuits for receiving input signals of high and low potential, Q and Q output buffer circuits having respective inputs operatively coupled to the respective J and K input circuits for controlling the state of the Q and Q output buffer circuits according to the input signals, each said Q and Q output buffer circuit comprising an output for delivering output signals of high and low potential, pullup transistor element for sourcing current to the output from a power supply, pulldown transistor element for sinking current from the output to low potential, and phase splitter transistor element coupled to the input and to the pullup and pulldown transistor elements for controlling the conducting states of the respective pullup and pulldown transistor elements, said TTL flip flop circuit further comprising a first cross feedback circuit including a first cross feedback transistor element operatively coupled between the J input circuit and a collector node of the phase splitter transistor element of the Q output buffer circuit, and a second cross feedback circuit including a second cross feedback transistor element operatively coupled between the K input circuit and a collector node of the phase splitter transistor element of the Q output buffer circuit, the improvement comprising: each Q and Q output buffer circuit comprising dual phase splitter transistor elements including an output phase splitter transistor element operatively coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements, and at least one secondary phase splitter transistor element operatively coupled in current mirror configuration with the output phase splitter transistor element, said secondary phase splitter transistor element having a collector node without direct connection to the pullup transistor element and output, a cross feedback circuit and cross feedback transistor element being operatively coupled to the collector node of the secondary phase splitter transistor element thereby separating the cross feedback transistor element from the pullup transistor element and output of the output buffer circuit to prevent feedback transistor breakdown when the output is at high potential.

Claim 27

A TTL JK flip flop circuit having J and K input circuits for receiving input signals of high and low potential, Q and Q output buffer circuits having respective inputs operatively coupled to the respective J and K input circuits for controlling the state of the Q and Q output buffer circuits according to the input signals, each said Q and Q output buffer circuit comprising an output for delivering output signals of high and low potential, pullup transistor element for sourcing current to the output from a power supply, pulldown transistor element for sinking current from the output to low potential, and phase splitter transistor element coupled to the input and to the pullup and pulldown transistor elements for controlling the conducting states of the respective pullup and pulldown transistor elements, said TTL flip flop circuit further comprising a first cross feedback circuit including a first cross feedback transistor element operatively coupled between the J input circuit and a collector node of the phase splitter transistor element of the Q output buffer circuit, and a second cross feedback circuit including a second cross feedback transistor element operatively coupled between the K input circuit and a collector node of the phase splitter transistor element of the Q output buffer circuit, the improvement comprising: each Q and Q output buffer circuit comprising dual phase splitter transistor elements including an output phase splitter transistor element operatively coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements, and at least one secondary phase splitter transistor element operatively coupled in current mirror configuration with the output phase splitter transistor element, said secondary phase splitter transistor element having a collector node without direct connection to the pullup transistor element and output, a cross feedback circuit and cross feedback transistor element being operatively coupled to the collector node of the secondary phase splitter transistor element thereby separating the cross feedback transistor element from the pullup transistor element and output of the output buffer circuit to prevent feedback transistor breakdown when the output is at high potential.

Claim 28

The TTL JK flip flop circuit of claim 21, wherein each Q and Q output buffer circuit further comprises a current sourcing transistor element operatively coupled in parallel with the cross feedback circuit at the collector node of the secondary phase splitter transistor element for supplying variable mirroring current which varies inversely with the cross feedback circuit collector load current to provide substantially equal emitter current densities at the emitters of the dual phase splitter transistor elements without current hogging at the base drives of the dual phase splitter transistor elements.

Claim 29

The TTL JK flip flop circuit of claim 22 wherein each output buffer circuit further comprises a current sourcing transistor bias circuit operatively coupled between the emitter of the current sourcing transistor element and ground for maintaining the current sourcing transistor clement in a slightly conducting state.

Claim 30

The TTL JK flip flop circuit of claim 22 wherein each output buffer circuit comprises an input transistor having an emitter coupled to the bases of the dual phase splitter transistor element and wherein the base of the current sourcing transistor element is coupled to the collector of the input transistor element.

Claim 31

The TTL JK flip flop circuit of claim 22 wherein the emitter area of the supplemental phase splitter transistor element is slightly larger than the emitter area of the output phase splitter transistor element.