US4956801A
Expired / Lapsed
US
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Matrix arithmetic circuit for processing matrix transformation operations
Assignee: Sun Microsystems Inc
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Filing: 1989-09-15
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Granted: 1990-09-11
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Expires: 2009-09-15
Abstract
Abstract A matrix arithmetic circuit for processing matrix transformation operations includes a random access memory (RAM) for storing a plurality of numbers in Modulo 256 with multiple tap points numbers format. A multiplier multiplies two of the Modulo 256 numbers in RAM to obtain a product. The product is normalized and added to a third Modulo 256 number stored in the RAM to obtain a result. The result is stored in the RAM and coupled to the data processing system for use in matrix transformation operations.
Inventors
- 👤 Curtis Priem
- 👤 Chris Malachowsky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:15
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
211 words
In a data processing system, an improved matrix arithmetic circuit for processing matrix transformation operations, comprising: random access memory means for receiving and storing a plurality of numbers in Modulo 256 with multiple tap points number format, said plurality of numbers being provided by an input conversion circuit coupled to said data processing system; multiplier means coupled to said memory means for multiplying first and second of said numbers stored in said memory means in Modulo 256 format, to form a first result, said result including an exponent; normalization means coupled to said multiplier means for normalizing said first result, said normalization means including shifting means for shifting said first result by eight bit increments as far to the left of the format space available as possible, and means for reducing said exponent of the result by one for each such shift; adder means coupled to said normalization means for adding said normalized first result to a third number in Modulo 256 with multiple tap points number format to obtain a second result; register means coupled to said adder means for receiving said second result and coupling said result to said memory means for storage, said second result also coupled to an output conversion circuit coupled to said data processing system.
Claim 2
Dependent Claim
211 words
In a data processing system, an improved matrix arithmetic circuit for processing matrix transformation operations, comprising: random access memory means for receiving and storing a plurality of numbers in Modulo 256 with multiple tap points number format, said plurality of numbers being provided by an input conversion circuit coupled to said data processing system; multiplier means coupled to said memory means for multiplying first and second of said numbers stored in said memory means in Modulo 256 format, to form a first result, said result including an exponent; normalization means coupled to said multiplier means for normalizing said first result, said normalization means including shifting means for shifting said first result by eight bit increments as far to the left of the format space available as possible, and means for reducing said exponent of the result by one for each such shift; adder means coupled to said normalization means for adding said normalized first result to a third number in Modulo 256 with multiple tap points number format to obtain a second result; register means coupled to said adder means for receiving said second result and coupling said result to said memory means for storage, said second result also coupled to an output conversion circuit coupled to said data processing system.
Claim 3
Dependent Claim
58 words
The matrix arithmetic circuit as defined by claim 1, wherein said third number includes an exponent and said adder means comprises a circuit for comparing said exponents from said normalized first result and said third number and equaling means for equaling said exponents by shifting the number having the least exponent to the right in eight bit increments.
Claim 4
Dependent Claim
17 words
The matrix arithmetic circuit as defined by claim 1, wherein said equaling means comprises a barrel shifter.
Claim 5
Dependent Claim
24 words
The matrix arithmetic circuit as defined by claim 3, further including second normalization means coupled to said adder means for normalizing said second result.
Claim 6
Dependent Claim
49 words
The matrix arithmetic circuit as defined by claim 4, wherein said second normalization means includes means for shifting the result by eight bit increments as far to the left of the format space available as possible and reducing the exponent of said second result by one of each shift.
Claim 7
Dependent Claim
37 words
A matrix arithmetic circuit as claimed in claim 1 in which the means for shifting the result by eight bit increments as far to the left of the format space available as possible comprises a barrel shifter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-10 | 1994-03-12 | 1994-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-10 | 1998-03-12 | 1998-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-10 | 2002-03-12 | 2002-09-11 | $7700.00 | Window Closed / Lapsed |