US4811268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processing circuit capable of raising throughput of accumulation
Assignee: NEC Corp
•
Filing: 1986-05-19
•
Granted: 1989-03-07
•
Expires: 2006-05-19
Abstract
Abstract In a processing circuit for successively accumulating a first predetermined number of products, each product is shifted in a barrel shifter (20) downwards by a second predetermined number of bits determined in relation to the first predetermined number and is successively added to a previous result of accumulation in an arithmetic/logic unit (ALU) (21) the first predetermined number of times to produce a final result of accumulation. The first result is shifted in a shifter (27) upwards by a third predetermined number of bits determined in relation to the second predetermined number. An overflow detector (26) monitors each result of accumulation to detect occurrence of an overflow in the ALU and the shifter to substitute either a positive or a negative maximum number for each result by an overflow corrector (25) on occurrence of the overflow. The substituted maximum number or the shifted final result is produced as an output signal.
Inventors
- 👤 Takao Nishitani
- 👤 Yuichi Kawakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:27
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/5443; G06F17/00; G06F17/10; G06F7/499; G06F7/49905; G06F7/4991; G06F7/49921
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
368 words
In a processing circuit comprising multiplication means for successively multiplying a sequence of first input data signals by a sequence of second input data signals to produce a sequence of product signals each of which is representative of a result of multiplication and summing means coupled to said multiplication means for successively summing up a first predetermined number of said product signals to produce a sum signal, each of said first and said second input data signals being represented by a fixed-point representation of a single precision bit length and arranged from a most significant bit to a least significant bit while each of said product signals is represented by the fixed-point representation of a double precision bit length and arranged from a most significant bit to a least significant bit, said sum signal being represented by the fixed-point representation of the single precision bit length, the improvement wherein said summing means comprises: first shifting means coupled to said multiplication means for shifting said each product signal towards the least significant bit of said each product signal by a second predetermined number of bits determined in relation to said first predetermined number to produce a succession of shifted product signals each of which has the double precision bit length; accumulating means coupled to said first shifting means for successively accumulating said first predetermined number of the shifted product signals to produce an accumulation signal representative of a result of accumulation, said accumulation signal having the double precision bit length and being arranged from a most significant bit to a least significant bit; second shifting means coupled to said accumulating means for shifting said accumulation signal towards the most significant bit of said accumulation signal by a third predetermined number of bits determined in relation to said second predetermined number to produce a shifted accumulation signal; overflow monitoring means coupled to said accumulating means and said second shifting means for monitoring occurrence of an overflow in said shifted accumulation signal to process said shifted accumulation signal and thereby to produce a processed signal which is representative of a result of monitoring and has the double precision bit length; and means for producing said processed signal as said sum signal.
Claim 2
Dependent Claim
368 words
In a processing circuit comprising multiplication means for successively multiplying a sequence of first input data signals by a sequence of second input data signals to produce a sequence of product signals each of which is representative of a result of multiplication and summing means coupled to said multiplication means for successively summing up a first predetermined number of said product signals to produce a sum signal, each of said first and said second input data signals being represented by a fixed-point representation of a single precision bit length and arranged from a most significant bit to a least significant bit while each of said product signals is represented by the fixed-point representation of a double precision bit length and arranged from a most significant bit to a least significant bit, said sum signal being represented by the fixed-point representation of the single precision bit length, the improvement wherein said summing means comprises: first shifting means coupled to said multiplication means for shifting said each product signal towards the least significant bit of said each product signal by a second predetermined number of bits determined in relation to said first predetermined number to produce a succession of shifted product signals each of which has the double precision bit length; accumulating means coupled to said first shifting means for successively accumulating said first predetermined number of the shifted product signals to produce an accumulation signal representative of a result of accumulation, said accumulation signal having the double precision bit length and being arranged from a most significant bit to a least significant bit; second shifting means coupled to said accumulating means for shifting said accumulation signal towards the most significant bit of said accumulation signal by a third predetermined number of bits determined in relation to said second predetermined number to produce a shifted accumulation signal; overflow monitoring means coupled to said accumulating means and said second shifting means for monitoring occurrence of an overflow in said shifted accumulation signal to process said shifted accumulation signal and thereby to produce a processed signal which is representative of a result of monitoring and has the double precision bit length; and means for producing said processed signal as said sum signal.
Claim 3
Dependent Claim
101 words
A processing circuit as claimed in claim 1, wherein said overflow monitoring means comprises: overflow detecting means coupled to said second shifting means for detecting occurrence of said overflow in said shifted accumulation signal to produce an overflow signal on occurrence of said overflow; and substituting means responsive to said shifted accumulation signal and coupled to said overflow detecting means for substituting a preselected signal for said shifted accumulation signal to produce said preselected signal as said processed signal when said overflow signal is received by said substituting means and, otherwise, for producing said shifted accumulation signal as said processed signal.
Claim 4
Dependent Claim
32 words
A processing circuit as claimed in claim 1, wherein said second predetermined number is a minimum integer L which is not smaller than: log.sub.2 M, where M represents said first predetermined number.
Claim 5
Dependent Claim
80 words
A processing circuit as claimed in claim 3, one of said first and said second input data signals standing for a first value which is not smaller than -2 K and is smaller than 2 K , where K is a natural number, while the other of said first and said second input data signals stands for a second value which is not smaller than -1 and is smaller than +1, wherein said third predetermined number is equal to: K+L.
Claim 6
Dependent Claim
44 words
A processing circuit as claimed in claim 1, wherein said second predetermined number is an integer L' which is smaller than a minimum integer L which is not smaller than: log.sub.2 M, where M is a natural number representative of said first predetermined number.
Claim 7
Dependent Claim
80 words
A processing circuit as claimed in claim 5, one of said first and said second input data signals standing for a first value which is not smaller than -2 K and is smaller than 2 K , where K is a natural number, while the other of said first and said second input data signals stands for a second value which is not smaller than -1 and is smaller than +1, wherein said third predetermined number is equal to: K+L'.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |