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US4956768A Expired / Lapsed US ⏱️ 0.0 years remaining

Wideband server, in particular for transmitting music or images

Assignee: France Telecom R&D SA
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Filing: 1988-02-24
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Granted: 1990-09-11
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Expires: 2008-02-24
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Abstract

Abstract A wideband server is defined by a main processor (10) communicating over a DMA channel (15) with a hard disk (16) and also with outlet cards (2-1 to 2-16). Each outlet card has its own processor which controls alternating mode to-processor access to two buffer memories A and B. While one of the buffer memories is delivering musical data to a user, the other is being filled, and vice versa.

Inventors

  • 👤 Jean A. Sidi
  • 👤 Claude B. Nogrady

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 12:29
CPC Classifications
H; H04; H04H; H04H20/00; H04H20/38; H04H20/65; H04H20/76; H04H20/82

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 140 words
An electronic apparatus suitable for constituting a wideband server, in particular for transmitting music or images, comprising in combination: a main processor possessing a direct memory access channel; a large capacity mass memory of the hard disk type, connected to said direct memory access channel; and a plurality of outlet units, operatively connected to said direct memory access channel and each possessing two buffer memories of equal capacity and an auxiliary processor operatively connected thereto, said buffer memories being dual-access memories operatively connected to said direct memory access channel and operated in alternating mode by said auxiliary processor to empty said buffer memories in alternation without discontinuity with one of said two buffer memories being read from while the other of said two buffer memories is simultaneously filled at high speed with new data from said large capacity mass memory.
Claim 2
Dependent Claim 140 words
An electronic apparatus suitable for constituting a wideband server, in particular for transmitting music or images, comprising in combination: a main processor possessing a direct memory access channel; a large capacity mass memory of the hard disk type, connected to said direct memory access channel; and a plurality of outlet units, operatively connected to said direct memory access channel and each possessing two buffer memories of equal capacity and an auxiliary processor operatively connected thereto, said buffer memories being dual-access memories operatively connected to said direct memory access channel and operated in alternating mode by said auxiliary processor to empty said buffer memories in alternation without discontinuity with one of said two buffer memories being read from while the other of said two buffer memories is simultaneously filled at high speed with new data from said large capacity mass memory.
Claim 3
Dependent Claim 28 words
An apparatus according to claim 1, wherein said buffer memories have a capacity of 128 kilobytes each, and are controlled by a 16-bit processor clocked at 8 MHz.
Claim 4
Dependent Claim 105 words
An apparatus according to claim 1, wherein the main processor is a 16-bit process clocked at 8 MHz, and manages a catalog situated on at least one hard disk of said mass memory, said mass memory having a head positioning time of not more than about 25 milliseconds for a read speed of about 2 megabytes per second, thereby enabling 128 kilobytes to be loaded into one of said buffer memories in less than 0.15 seconds, and consequently enabling 16 of said outlet units to output data without discontinuity, with each of said outlet units delivering their respective data at about 48 kilobytes per second.
Claim 5
Dependent Claim 23 words
An apparatus according to claim 1, wherein said outlet units each comprise data decoding means for decoding data read from said buffer memories.
Claim 6
Dependent Claim 54 words
An apparatus according to claim 1, further comprising a serial interface, operatively connected to said main processor and to receive data for storage in said mass memory, and wherein said mass memory stores the data received by said serial interface at distributed areas having a size determined by the capacity of said buffer memories.
Claim 7
Dependent Claim 45 words
An apparatus according to claim 5, further comprising interface means for receiving data, to be stored in said mass memory, from a general server center over a digital network having a binary data rate of between 64 kilobits per second and two megabits per second.
Claim 8
Dependent Claim 28 words
An apparatus according to claim 1, wherein said outlet units are connected to consultation stations to supply at least one of music and images to the consultation stations.
Claim 9
Dependent Claim 46 words
An apparatus according to claim 7, further comprising telematic server means for communicating with users via Minitels, enabling a piece of music or a set of images to be selected by the users from said wideband server and supplied to the users via said outlet units.
Claim 10
Dependent Claim 24 words
An apparatus according to claim 7, wherein a plurality of the consultation stations can simultaneously receive at least one of musical and video data.
Claim 11
Dependent Claim 24 words
An apparatus according to claim 8, wherein a plurality of the consultation stations can simultaneously receive at least one of musical and video data.
Claim 12
Dependent Claim 15 words
An apparatus according to claim 5, wherein said outlet data decoding means performs digital-to-analog conversion.
Claim 13
Dependent Claim 30 words
An apparatus according to claim 6, wherein the digital network is at least one of a video communications network, an integrated service digital network and a network served by satellite.
Claim 14
Dependent Claim 46 words
An apparatus according to claim 7, further comprising telematic server means for communicating with users via computer terminals, enabling a piece of music or a set of images to be selected by users from said wideband server and supplied to the users via said outlet units.
Claim 15
Dependent Claim 117 words
An electronic apparatus, comprising: a main processor; a direct memory access channel for wideband transmission of data; a high-speed large capacity mass memory connected to said direct memory access channel; and a plurality of outlet units for receiving the wideband transmission of data via said direct memory access channel, each of said outlet units including at least two dual-access buffer memories, each operatively connected to said direct memory access channel; and an auxiliary processor for controlling access to said dual-access buffer memories so that one of said dual-access buffer memories is receiving data from said direct memory access channel while another of said dual-access buffer memories is inputting data, thereby enabling wideband transmission of data without discontinuity.
Claim 16
Dependent Claim 117 words
An electronic apparatus, comprising: a main processor; a direct memory access channel for wideband transmission of data; a high-speed large capacity mass memory connected to said direct memory access channel; and a plurality of outlet units for receiving the wideband transmission of data via said direct memory access channel, each of said outlet units including at least two dual-access buffer memories, each operatively connected to said direct memory access channel; and an auxiliary processor for controlling access to said dual-access buffer memories so that one of said dual-access buffer memories is receiving data from said direct memory access channel while another of said dual-access buffer memories is inputting data, thereby enabling wideband transmission of data without discontinuity.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-09-10 1994-03-12 1994-09-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-09-10 1998-03-12 1998-09-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-09-10 2002-03-12 2002-09-11 $7700.00 Window Closed / Lapsed

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