Differential amplifier having externally controllable power consumption

Claim 2

A differential amplifier having first and second parallel circuit branches each of which contains a load element (L1, L2) and a field effect transistor (T1, T2), respectively, and having a field effect transistor (T3) serving as a current source that is connected via a first circuit node to the first and second parallel circuit branches (L1, T1; L2, T2) and whose gate terminal is connected to a bias that defines the quiescent currents flowing in these circuit branches, comprising a circuit stage for setting the quiescent currents having an output-side resistor connected to a gate terminal of the field effect transistor (T3) serving as the current source; two additional field effect transistors (T10, T11) of a p-channel type connected in series with the output-side resistor; and a level-converting circuit having an input connected to gate terminals of the field effect transistors (T1, T2) in the parallel circuit branches, that, further, converts the DC part of an input signal to a higher output level that roughly corresponds to the value of the threshold voltage of the two additional field effect transistors (T10, T11) and that has an output side connected to gate terminals of the two additional field effect transistors (T10, T11).

Claim 3

The differential amplifier according to claim 1, wherein the circuit stage for setting the quiescent currents is composed of a series circuit of two field effect transistors (T8, T9) of different channel types; wherein a gate of one of these field effect transistors (T8) is connected to a fixed bias and wherein the other transistor (T9) is the output-side resistor, whereby a gate terminal of the other transistor (T9) is connected to one of its other terminals, such other terminals of the other transistor (T9) being a source terminal and a drain terminal, as well as to the gate terminal of the field effect transistor (T3) serving as the current source.

Claim 4

The differential amplifier according to claim 1, wherein the level-converting circuit is composed of a differential amplifier stage that contains two current branches of which each has a series circuit of two field effect transistors (T12, T13, and T14, T15, respectively) of different channel types; wherein a current source transistor (T16) of one channel type is connected via a second circuit node to these two current branches; wherein gate terminals of the field effect transistors (T13, T15) of the current branches that correspond to the channel type of the current source transistor (T16) form the circuit inputs (9, 8) of the level-converting circuit; wherein the junctions between the field effect transistors (T13, T15) and the other two field effect transistors (T12, T14) of the current branches are the circuit outputs (10, 11) of the level-converting circuit; and wherein these other two field effect transistors (T12, T14) operate in a triode range, whereas the current source transistor (T16) is operated in a saturation range.

Claim 5

A differential amplifier having first and second parallel circuit branches each of which contains a load element (L1, L2) and a field effect transistor (T1, T2), respectively and having a field effect transistor (T3) serving as a current source that is connected via a first circuit node to the first and second parallel circuit branches (L1, T1; L2, T2) and whose gate terminal is connected to a bias that defines the quiescent currents flowing in these circuit branches, comprising a circuit stage for setting the quiescent currents having an output-side resistor connected to a gate terminal of the field effect transistor (T3) serving as the current source; two additional field effect transistors (T10, T11) of an n-channel type connected in series with the output-side resistor; and a level-converting circuit having an input connected to gate terminals of the field effect transistors (T1, T2) in the parallel circuit branches, that, further, converts the DC part of an input signal to a lower output level that roughly corresponds to the value of the threshold voltage of the two additional field effect transistors (T10, T11) and that has an output side connected to gate terminals of the two additional field effect transistors (T10, T11).

Claim 6

A differential amplifier having first and second parallel circuit branches each of which contains a load element (L1, L2) and a field effect transistor (T1, T2), respectively and having a field effect transistor (T3) serving as a current source that is connected via a first circuit node to the first and second parallel circuit branches (L1, T1; L2, T2) and whose gate terminal is connected to a bias that defines the quiescent currents flowing in these circuit branches, comprising a circuit stage for setting the quiescent currents having an output-side resistor connected to a gate terminal of the field effect transistor (T3) serving as the current source; two additional field effect transistors (T10, T11) of an n-channel type connected in series with the output-side resistor; and a level-converting circuit having an input connected to gate terminals of the field effect transistors (T1, T2) in the parallel circuit branches, that, further, converts the DC part of an input signal to a lower output level that roughly corresponds to the value of the threshold voltage of the two additional field effect transistors (T10, T11) and that has an output side connected to gate terminals of the two additional field effect transistors (T10, T11).

Claim 7

The differential amplifier according to claim 4, wherein the circuit stage for setting the quiescent currents is composed of a series circuit of two field effect transistors (T8, T9) of different channel types; wherein a gate of one of these field effect transistors (T8) is connected to a fixed bias and wherein the other transistor (T9) is the output-side resistor, whereby a gate terminal of the other transistor (T9) is connected to one of its other terminals, such other terminals of the other transistor (T9) being a source terminal and a drain terminal, as well as to the gate terminal of the field effect transistor (T3) serving as the current source.

Claim 8

The differential amplifier according to claim 4, wherein the level-converting circuit is composed of a differential amplifier stage that contains two current branches of which each has a series circuit of two field effect transistors (T12, T13, and T14, T15, respectively) of different channel types; wherein a current source transistor (T16) of one channel type is connected via a second circuit node to these two current branches; wherein gate terminals of the field effect transistors (T13, T15) of the current branches that correspond to the channel type of the current source transistor (T16) form the circuit inputs (9, 8) of the level-converting circuit; wherein the junctions between the field effect transistors (T13, T15) and the other two field effect transistors (T12, T14) of the current branches are the circuit outputs (10, 11) of the level-converting circuit; and wherein these other two field effect transistors (T12, T14) operate in a triode range, whereas the current source transistor (T16) is operated in a saturation range.

Claim 9

A differential amplifier having first and second parallel circuit branches each of which contains a load element (L1, L2), the load elements L1 and L2 being p-channel field effect transistors, and an n-channel field effect transistor (T1, T2), respectively, and having an n-channel field effect transistor (T3) serving as a current source that is connected via a first circuit node to the first and second parallel circuit branches (L1, T1; L2, T2) and whose gate terminal is connected to a bias that defines the quiescent currents flowing in these circuit branches, comprising: a circuit stage for setting the quiescent currents having an output-side resistor, the output-side resistor being an n-channel field effect transistor (T9), connected to a gate terminal of the field effect transistor (T3) serving as the current source; two additional p-channel field effect transistors (T10, T11) connected in series with the output-side resistor; and a level-converting circuit having an input connected to gate terminals of the field effect transistors (T1, T2) in the parallel circuit branches, that, further, converts the DC part of an input signal to a higher output level that roughly corresponds to the value of the threshold voltage of the two additional field effect transistors (T10, T11) and that has an output side connected to gate terminals of the two additional field effect transistors (T10, T11); the circuit stage for setting the quiescent currents being composed of a series circuit of a p-channel field effect transistor (T8) and the n-channel field effect transistor (T9); wherein a gate of the p-channel field effect transistor (T8) is connected to a fixed bias, whereby a gate terminal of the n-channel field effect transistor (T9) is connected to one of its other terminals, such other terminals of the n-channel field effect transistor (T9) being a source terminal and a drain terminal, as well as to the gate terminal of the field effect transistor (T3) serving as the current source; and the level-converting circuit being composed of a differential amplifier stage that contains two current branches of which each has a series circuit of two field effect transistors (T12, T13, and T14, T15, respectively), transistors T12 and T14 being p-channel field effect transistors and transistors T13 and T15 being n-channel field effect transistors, wherein a current source n-channel field effect transistor (T16) is connected via a second circuit node to these two current branches; wherein gate terminals of the field effect transistors (T13, T15) of the current branches that correspond to the channel type of the current source transistor (T16) form the circuit inputs (9, 8) of the level-converting circuit; wherein the junctions between the field effect transistors (T13, T15) and the other two field effect transistors (T12, T14) of the current branches are the circuit outputs (10, 11) of the level-converting circuit; and wherein these other two field effect transistors (T12, T14) operate in a triode range, whereas the current source transistor (T16) is operated in a saturation range.

Claim 10

A differential amplifier having first and second parallel circuit branches each of which contains a load element (L1, L2), the load elements L1 and L2 being p-channel field effect transistors, and an n-channel field effect transistor (T1, T2), respectively, and having an n-channel field effect transistor (T3) serving as a current source that is connected via a first circuit node to the first and second parallel circuit branches (L1, T1; L2, T2) and whose gate terminal is connected to a bias that defines the quiescent currents flowing in these circuit branches, comprising: a circuit stage for setting the quiescent currents having an output-side resistor, the output-side resistor being an n-channel field effect transistor (T9), connected to a gate terminal of the field effect transistor (T3) serving as the current source; two additional p-channel field effect transistors (T10, T11) connected in series with the output-side resistor; and a level-converting circuit having an input connected to gate terminals of the field effect transistors (T1, T2) in the parallel circuit branches, that, further, converts the DC part of an input signal to a higher output level that roughly corresponds to the value of the threshold voltage of the two additional field effect transistors (T10, T11) and that has an output side connected to gate terminals of the two additional field effect transistors (T10, T11); the circuit stage for setting the quiescent currents being composed of a series circuit of a p-channel field effect transistor (T8) and the n-channel field effect transistor (T9); wherein a gate of the p-channel field effect transistor (T8) is connected to a fixed bias, whereby a gate terminal of the n-channel field effect transistor (T9) is connected to one of its other terminals, such other terminals of the n-channel field effect transistor (T9) being a source terminal and a drain terminal, as well as to the gate terminal of the field effect transistor (T3) serving as the current source; and the level-converting circuit being composed of a differential amplifier stage that contains two current branches of which each has a series circuit of two field effect transistors (T12, T13, and T14, T15, respectively), transistors T12 and T14 being p-channel field effect transistors and transistors T13 and T15 being n-channel field effect transistors, wherein a current source n-channel field effect transistor (T16) is connected via a second circuit node to these two current branches; wherein gate terminals of the field effect transistors (T13, T15) of the current branches that correspond to the channel type of the current source transistor (T16) form the circuit inputs (9, 8) of the level-converting circuit; wherein the junctions between the field effect transistors (T13, T15) and the other two field effect transistors (T12, T14) of the current branches are the circuit outputs (10, 11) of the level-converting circuit; and wherein these other two field effect transistors (T12, T14) operate in a triode range, whereas the current source transistor (T16) is operated in a saturation range.

Claim 11

A differential amplifier having first and second parallel circuit branches each of which contains a load element (L1, L2), the load elements L1 and L2 being n-channel field effect transistors, and a p-channel field effect transistor (T1, T2), respectively, and having a p-channel field effect transistor (T3) serving as a current source that is connected via a first circuit node to the first and second parallel circuit branches (L1, T1; L2, T2) and whose gate terminal is connected to a bias that defines the quiescent currents flowing in these circuit branches, comprising: a circuit stage for setting the quiescent currents having an output-side resistor, the output-side resistor being a p-channel field effect transistor (T9), connected to a gate terminal of the field effect transistor (T3) serving as the current source; two additional n-channel field effect transistors (T10, T11) connected in series with the output-side resistor; and a level-converting circuit having an input connected to gate terminals of the field effect transistors (T1, T2) in the parallel circuit branches, that, further, converts the DC part of an input signal to a lower output level that roughly corresponds to the value of the threshold voltage of the two additional field effect transistors (T10, T11) and that has an output side connected to gate terminals of the two additional field effect transistors (T10, T11); the circuit stage for setting the quiescent currents being composed of a series circuit of an n-channel field effect transistor (T8) and the p-channel field effect transistor (T9); wherein a gate of the n-channel field effect transistor (T8) is connected to a fixed bias, whereby a gate terminal of the p-channel field effect transistor (T9) is connected to one of its other terminals, such other terminals of the p-channel field effect transistor (T9) being a source terminal and a drain terminal, as well as to the gate terminal of the field effect transistor (T3) serving as the current source; and the level-converting circuit being composed of a differential amplifier stage that contains two current branches of which each has a series circuit of two field effect transistors (T12, T13, and T14, T15, respectively), transistor T12 and T14 being n-channel field effect transistors and transistors T13 and T15 being p-channel field effect transistors, wherein a current source p-channel field effect transistor (T16) is connected via a second circuit node to these two current branches; wherein gate terminals of the field effect transistors (T13, T15) of the current branches that correspond to the channel type of the current source transistor (T16) form the circuit inputs (9, 8) of the level-converting circuit; wherein the junctions between the field effect transistors (T13, T15) and the other two field effect transistors (T12, T14) of the current branches are the circuit outputs (10, 11) of the level-converting circuit; and wherein these other two field effect transistors (T12, T14) operate in a triode range, whereas the current source transistor (T16) is operated in a saturation range.

Claim 12

A differential amplifier having first and second parallel circuit branches each of which contains a load element (L1, L2), the load elements L1 and L2 being n-channel field effect transistors, and a p-channel field effect transistor (T1, T2), respectively, and having a p-channel field effect transistor (T3) serving as a current source that is connected via a first circuit node to the first and second parallel circuit branches (L1, T1; L2, T2) and whose gate terminal is connected to a bias that defines the quiescent currents flowing in these circuit branches, comprising: a circuit stage for setting the quiescent currents having an output-side resistor, the output-side resistor being a p-channel field effect transistor (T9), connected to a gate terminal of the field effect transistor (T3) serving as the current source; two additional n-channel field effect transistors (T10, T11) connected in series with the output-side resistor; and a level-converting circuit having an input connected to gate terminals of the field effect transistors (T1, T2) in the parallel circuit branches, that, further, converts the DC part of an input signal to a lower output level that roughly corresponds to the value of the threshold voltage of the two additional field effect transistors (T10, T11) and that has an output side connected to gate terminals of the two additional field effect transistors (T10, T11); the circuit stage for setting the quiescent currents being composed of a series circuit of an n-channel field effect transistor (T8) and the p-channel field effect transistor (T9); wherein a gate of the n-channel field effect transistor (T8) is connected to a fixed bias, whereby a gate terminal of the p-channel field effect transistor (T9) is connected to one of its other terminals, such other terminals of the p-channel field effect transistor (T9) being a source terminal and a drain terminal, as well as to the gate terminal of the field effect transistor (T3) serving as the current source; and the level-converting circuit being composed of a differential amplifier stage that contains two current branches of which each has a series circuit of two field effect transistors (T12, T13, and T14, T15, respectively), transistor T12 and T14 being n-channel field effect transistors and transistors T13 and T15 being p-channel field effect transistors, wherein a current source p-channel field effect transistor (T16) is connected via a second circuit node to these two current branches; wherein gate terminals of the field effect transistors (T13, T15) of the current branches that correspond to the channel type of the current source transistor (T16) form the circuit inputs (9, 8) of the level-converting circuit; wherein the junctions between the field effect transistors (T13, T15) and the other two field effect transistors (T12, T14) of the current branches are the circuit outputs (10, 11) of the level-converting circuit; and wherein these other two field effect transistors (T12, T14) operate in a triode range, whereas the current source transistor (T16) is operated in a saturation range.