US4955061A
Expired / Lapsed
US
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Method and apparatus for processing an image signal
Assignee: Sony Corp
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Filing: 1988-12-06
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Granted: 1990-09-04
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Expires: 2008-12-06
Abstract
Abstract An apparatus for compressed encoding or decoding of a binary image signal and outputting the same wherein both the encoder and the decoder employ counters which are caused to run at a faster than normal rate when certain predetermined conditions relative to the processed data are detected.
Inventors
- 👤 Tetsuo Doi
- 👤 Takeshi Funabashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:04
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/41; H04N1/411; H04N1/413; H04N1/417; H04N1/4175
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
192 words
An apparatus for processing an image signal comprising: data input circuit means for receiving input image data having first and second binary values; encoding circuit means for encoding said input image data into compressed code data; and data output circuit means for outputting said compressed code data, wherein said encoding circuit means includes (i) first detecting circuit means for detecting transition points where the value of said input image data changes from one to another of said first and second binary values, (ii) counter means for generating addresses of said transition points of said input image data, (iii) second detecting circuit means for detecting if the value of said input image data does not change during a time period exceeding a predetermined period, (iv) control means for controlling said counter means so as to count at a faster than normal speed until a predetermined number is reached during each predetermined period when the value of the input image data does not change during a period exceeding the predetermined period, and (v) encoder means for encoding said input image data by using said addresses of said transition points of said input image data.
Claim 2
Independent Claim
192 words
An apparatus for processing an image signal comprising: data input circuit means for receiving input image data having first and second binary values; encoding circuit means for encoding said input image data into compressed code data; and data output circuit means for outputting said compressed code data, wherein said encoding circuit means includes (i) first detecting circuit means for detecting transition points where the value of said input image data changes from one to another of said first and second binary values, (ii) counter means for generating addresses of said transition points of said input image data, (iii) second detecting circuit means for detecting if the value of said input image data does not change during a time period exceeding a predetermined period, (iv) control means for controlling said counter means so as to count at a faster than normal speed until a predetermined number is reached during each predetermined period when the value of the input image data does not change during a period exceeding the predetermined period, and (v) encoder means for encoding said input image data by using said addresses of said transition points of said input image data.
Claim 3
Independent Claim
135 words
An apparatus for processing an image signal comprising: data input circuit means for receiving compressed code data; decoding circuit means for decoding said input compressed code data into output image data to be outputted; and data output circuit means for outputting output image data, wherein said decoding circuit means includes (i) counter means for presetting a run length of said input compressed code data, (ii) detecting circuit means for detecting if the run length of said input compressed code data exceeds a predetermined number, (iii) control means for controlling said counter means so as to count at a faster than normal speed when the run length of said input compressed code data exceeds a predetermined number, and (iv) decoder means for generating binary image data according to said run length preset in said counter means.
Claim 4
Independent Claim
135 words
An apparatus for processing an image signal comprising: data input circuit means for receiving compressed code data; decoding circuit means for decoding said input compressed code data into output image data to be outputted; and data output circuit means for outputting output image data, wherein said decoding circuit means includes (i) counter means for presetting a run length of said input compressed code data, (ii) detecting circuit means for detecting if the run length of said input compressed code data exceeds a predetermined number, (iii) control means for controlling said counter means so as to count at a faster than normal speed when the run length of said input compressed code data exceeds a predetermined number, and (iv) decoder means for generating binary image data according to said run length preset in said counter means.
Claim 5
Dependent Claim
339 words
Apparatus for processing lines of image data comprising: a data input/output circuit for receiving and outputting binary image data and compressed code data; an encoding circuit including (i) a first detecting circuit for detecting transition points where the value of an input binary image data changes from one to another, (ii) an up-counter for generating addresses of the transition points, (iii) a second detecting circuit for detecting if the value of the input binary image data does not change during a predetermined period so as to control the up-counter so as to count up faster than at a normal speed and (iv) means for encoding the input image data into the output compressed code data by using the correlation between a preceding line, used as a reference line, and a subsequent, encoding line based on the addresses of the transition points, a decoding circuit including a down-counter for presetting a run length of the input compressed code data and a third detecting circuit for detecting if the run length of the input compressed code data exceeds a predetermined number, means for controlling the down-counter so as to count down faster than at a normal speed, whereby the input compressed code data is decoded into the output binary image data, a pair of data memories for storing the addresses of the transition points of selected lines of image data; control circuit means for causing one of the data memories to be in a write status while the other is in a read status and for alternately changing the write and read statuses for every line to read out or write the addresses of the transition points of a preceding line from or into one of the data memories and the addresses of the transition points of an encoding or decoding line from or into the other memory, a microprocessor, including program memories, for selectively causing the encoding and decoding means to operate so that the data input/output circuit selectively receives or outputs binary image data and the compressed code data.
Claim 6
Dependent Claim
339 words
Apparatus for processing lines of image data comprising: a data input/output circuit for receiving and outputting binary image data and compressed code data; an encoding circuit including (i) a first detecting circuit for detecting transition points where the value of an input binary image data changes from one to another, (ii) an up-counter for generating addresses of the transition points, (iii) a second detecting circuit for detecting if the value of the input binary image data does not change during a predetermined period so as to control the up-counter so as to count up faster than at a normal speed and (iv) means for encoding the input image data into the output compressed code data by using the correlation between a preceding line, used as a reference line, and a subsequent, encoding line based on the addresses of the transition points, a decoding circuit including a down-counter for presetting a run length of the input compressed code data and a third detecting circuit for detecting if the run length of the input compressed code data exceeds a predetermined number, means for controlling the down-counter so as to count down faster than at a normal speed, whereby the input compressed code data is decoded into the output binary image data, a pair of data memories for storing the addresses of the transition points of selected lines of image data; control circuit means for causing one of the data memories to be in a write status while the other is in a read status and for alternately changing the write and read statuses for every line to read out or write the addresses of the transition points of a preceding line from or into one of the data memories and the addresses of the transition points of an encoding or decoding line from or into the other memory, a microprocessor, including program memories, for selectively causing the encoding and decoding means to operate so that the data input/output circuit selectively receives or outputs binary image data and the compressed code data.
Claim 7
Independent Claim
165 words
A method for processing an image signal comprising the steps of: receiving input image data having first and second binary values; encoding said input image data into compressed code data; outputting said compressed code data, wherein the encoding step includes (i) detecting transition points where the value of said input image data changes from one to another of said first and second binary values, (ii) generating addresses of said transition points of said input image data by advancing the count in a counter, (iii) detecting if the value of said input image data does not change during a time period exceeding a predetermined period, (iv) advancing the count in the counter at a faster than normal speed until a predetermined number is reached during each predetermined period when the value of the input image data does not change during a period exceeding the predetermined period, and (v) encoding said input image data by using said addresses of said transition points of said input image data.
Claim 8
Independent Claim
165 words
A method for processing an image signal comprising the steps of: receiving input image data having first and second binary values; encoding said input image data into compressed code data; outputting said compressed code data, wherein the encoding step includes (i) detecting transition points where the value of said input image data changes from one to another of said first and second binary values, (ii) generating addresses of said transition points of said input image data by advancing the count in a counter, (iii) detecting if the value of said input image data does not change during a time period exceeding a predetermined period, (iv) advancing the count in the counter at a faster than normal speed until a predetermined number is reached during each predetermined period when the value of the input image data does not change during a period exceeding the predetermined period, and (v) encoding said input image data by using said addresses of said transition points of said input image data.
Claim 9
Independent Claim
106 words
A method of processing an image signal comprising the steps of: receiving compressed code data; decoding said received compressed code data; and outputting output image data, wherein said decoding step includes (i) presetting a counter with a run length of said input compressed code data, (ii) detecting if the run length of said input compressed code data exceeds a predetermined number, (iii) controlling said counter means so as to count at a faster than normal speed when the run length of said input compressed code data exceeds a predetermined number, and (iv) generating binary image data according to said run length preset in said counter means.
Claim 10
Independent Claim
106 words
A method of processing an image signal comprising the steps of: receiving compressed code data; decoding said received compressed code data; and outputting output image data, wherein said decoding step includes (i) presetting a counter with a run length of said input compressed code data, (ii) detecting if the run length of said input compressed code data exceeds a predetermined number, (iii) controlling said counter means so as to count at a faster than normal speed when the run length of said input compressed code data exceeds a predetermined number, and (iv) generating binary image data according to said run length preset in said counter means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |