Patent US4954990A successfully refreshed from Google Patents.
US4954990A
Expired / Lapsed
US
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Programming voltage control circuit for EPROMS
Assignee: Cypress Semiconductor Corp
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Filing: 1989-05-30
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Granted: 1990-09-04
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Expires: 2009-05-30
Abstract
Abstract Apparatus for controlling the programming voltage of an EPROM array composed of a plurality of programmable floating gate MOS cells, which includes an additional floating gate MOS cell fabricated on the same chip and in the same manner as the array of cells, the additional cell not being connected for programming during the normal programming of the array. A voltage is applied to the additional cell to generate a drain current through the cell. A feedback control is connected between the source of external programming voltage for the array and the actual voltage within the array used for programming the cells, the feedback control using the amplitude of the drain current in the additional cell to control the magnitude of the actual programming voltage in the array in such a manner that when the drain current of the additional cell increases, the programming voltage decreases proportionately. The drain current in the additional cell can also be used for compensating for variations in the fixed programming voltage.
Inventors
- 👤 Dov-Ami Vider
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:34
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
124 words
Apparatus for controlling the programming voltage of an EPROM array having a plurality of programmable floating gate MOS cells, comprising: an additional floating gate MOS cell fabricated on the same chip in the same manner as said plurality of programmable floating gate cells, said additional cell not being connected for programming during normal programming of said array; means for applying a voltage to said additional cell in order to generate a drain current through said additional cell; feedback means coupled to a source of programming voltage for said array which uses the amplitude of said drain current in said additional cell to control the magnitude of said programming voltage in such a manner that when said drain current increases, said programming voltage proportionately decreases.
Claim 2
Dependent Claim
124 words
Apparatus for controlling the programming voltage of an EPROM array having a plurality of programmable floating gate MOS cells, comprising: an additional floating gate MOS cell fabricated on the same chip in the same manner as said plurality of programmable floating gate cells, said additional cell not being connected for programming during normal programming of said array; means for applying a voltage to said additional cell in order to generate a drain current through said additional cell; feedback means coupled to a source of programming voltage for said array which uses the amplitude of said drain current in said additional cell to control the magnitude of said programming voltage in such a manner that when said drain current increases, said programming voltage proportionately decreases.
Claim 3
Dependent Claim
48 words
The apparatus for controlling the programming voltage of an EPROM array of claim 1 further characterized by said feedback means including a current mirror circuit whose input is said drain current, said current mirror circuit coupling said additional cell to said source of programming voltage for said array.
Claim 4
Dependent Claim
169 words
Apparatus for controlling the programming voltage of an EPROM array having a plurality of programmable floating gate cells, comprising: an additional floating gate MOS cell fabricated on the same chip in the same manner as said plurality of programmable floating gate MOS cells, said additional cell not being connected for programming during normal programming of said array; a means for providing a predetermined voltage to said array, said predetermined voltage tending to vary somewhat with changes in ambient and processing conditions; means for coupling said predetermined voltage to said additional cell in order to generate a drain current through said additional cell, said drain current varying in accordance with the variations in said predetermined voltage; and feedback means coupling said additional cell to a source of programming voltage for said array, said feedback means using the amplitude of said drain current in said additional cell to control said programming voltage for said array in such a manner that when said predetermined voltage changes, said programming voltage remains substantially constant.
Claim 5
Dependent Claim
169 words
Apparatus for controlling the programming voltage of an EPROM array having a plurality of programmable floating gate cells, comprising: an additional floating gate MOS cell fabricated on the same chip in the same manner as said plurality of programmable floating gate MOS cells, said additional cell not being connected for programming during normal programming of said array; a means for providing a predetermined voltage to said array, said predetermined voltage tending to vary somewhat with changes in ambient and processing conditions; means for coupling said predetermined voltage to said additional cell in order to generate a drain current through said additional cell, said drain current varying in accordance with the variations in said predetermined voltage; and feedback means coupling said additional cell to a source of programming voltage for said array, said feedback means using the amplitude of said drain current in said additional cell to control said programming voltage for said array in such a manner that when said predetermined voltage changes, said programming voltage remains substantially constant.
Claim 6
Dependent Claim
52 words
The apparatus for controlling the programming voltage of an EPROM array of claim 3 further characterized by said means for coupling said predetermined voltage to said additional cell being a set of series-coupled resistors coupled between the gate or drain of said additional cell and said means for providing said predetermined voltage.
Claim 7
Dependent Claim
48 words
The apparatus for controlling the programming voltage of an EPROM array of claim 3 further characterized by said feedback means including a current mirror circuit whose input is said drain current, said current mirror circuit coupling said additional cell to said source of programming voltage for said array.
Claim 8
Dependent Claim
48 words
The apparatus for controlling the programming voltage of an EPROM array of claim 4 further characterized by said feedback means including a current mirror circuit whose input is said drain current, said current mirror circuit coupling said additional cell to said source of programming voltage for said array.
References Cited (Backward Citations)
US4791607A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |