US4952826A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal input circuit utilizing flip-flop circuit
Assignee: NEC Corp
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Filing: 1988-06-03
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Granted: 1990-08-28
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Expires: 2008-06-03
Abstract
Abstract A signal input circuit of a type in which an input signal voltage is compared with a reference voltage is disclosed. A first gate is connected in series with a first input transistor between a first terminal of an input amplifier comprising a flip-flop circuit and a reference terminal. A second gate is connected in series with a second input transistor between a second terminal of the input amplifier and the reference terminal. The first and second gates are controlled by potentials at third and fourth terminals of the input amplifier. The input terminals of an output amplifier are coupled to the first and second terminals of the input amplifier to provide output signals.
Inventors
- 👤 Katsuji Hoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:05
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/356069
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
411 words
A transistor circuit comprising a first insulated-gate field effect transistor having a gate supplied with an input signal voltage; a second insulated-gate field effect transistor having a gate supplied with a reference voltage; a first circuit of a flip-flop type including first and second input/output terminals, first and second common nodes, a third insulated-gate field effect transistor having a source-drain path connected between said first input/output terminal and said first common node and a gate connected to said second input/output terminal, a fourth insulated-gate field effect transistor having a source-drain path connected between said second input/output terminal and said first common node and a gate connected to said first input/output terminal, a fifth insulated-gate field effect transistor having a source-drain path connected between said first input/output terminal and said second common node, and a sixth insulated field effect transistor having a source-drain path connected between said second input/output terminal and said second common node; a second circuit including first and second input terminals, first and second output terminals, third and fourth common nodes, a seventh insulated-gate field effect transistor having a source-drain path connected between said first output terminal and said third common node and a gate connected to said first input terminal, an eighth insulated-gate field effect transistor having a source-drain path connected between said second output terminal and said third common node and a gate connected to said second input terminal, a ninth insulated-gate field effected transistor having a source-drain path connected between said first output terminal and said fourth common node, a tenth insulated-gate field effect transistor having a source-drain path connected between said second output terminal and said fourth common node, means for connecting said first and second input terminals to said first and second input/output terminals of said first circuit, respectively, and means for connecting said first and second output terminals to gates of said sixth and fifth transistors, respectively; an eleventh insulated-gate field effect transistor having a gate connected to said second output terminal of said second circuit; a twelfth insulated-gate field effect transistor having a gate connected to said first output terminal of said second circuit; a reference terminal; means for connecting said source-drain paths of said first and eleventh transistors in series between said second input/output terminal of said first circuit and said reference terminal; and means for connecting said source-drain paths of said second and twelfth transistors in series between said first input/output terminal of said first circuit and said reference terminal.
Claim 2
Dependent Claim
411 words
A transistor circuit comprising a first insulated-gate field effect transistor having a gate supplied with an input signal voltage; a second insulated-gate field effect transistor having a gate supplied with a reference voltage; a first circuit of a flip-flop type including first and second input/output terminals, first and second common nodes, a third insulated-gate field effect transistor having a source-drain path connected between said first input/output terminal and said first common node and a gate connected to said second input/output terminal, a fourth insulated-gate field effect transistor having a source-drain path connected between said second input/output terminal and said first common node and a gate connected to said first input/output terminal, a fifth insulated-gate field effect transistor having a source-drain path connected between said first input/output terminal and said second common node, and a sixth insulated field effect transistor having a source-drain path connected between said second input/output terminal and said second common node; a second circuit including first and second input terminals, first and second output terminals, third and fourth common nodes, a seventh insulated-gate field effect transistor having a source-drain path connected between said first output terminal and said third common node and a gate connected to said first input terminal, an eighth insulated-gate field effect transistor having a source-drain path connected between said second output terminal and said third common node and a gate connected to said second input terminal, a ninth insulated-gate field effected transistor having a source-drain path connected between said first output terminal and said fourth common node, a tenth insulated-gate field effect transistor having a source-drain path connected between said second output terminal and said fourth common node, means for connecting said first and second input terminals to said first and second input/output terminals of said first circuit, respectively, and means for connecting said first and second output terminals to gates of said sixth and fifth transistors, respectively; an eleventh insulated-gate field effect transistor having a gate connected to said second output terminal of said second circuit; a twelfth insulated-gate field effect transistor having a gate connected to said first output terminal of said second circuit; a reference terminal; means for connecting said source-drain paths of said first and eleventh transistors in series between said second input/output terminal of said first circuit and said reference terminal; and means for connecting said source-drain paths of said second and twelfth transistors in series between said first input/output terminal of said first circuit and said reference terminal.
Claim 3
Dependent Claim
60 words
The transistor circuit as claimed in claim 1, wherein said first and third common nodes are connected to said reference terminal, said second common node being supplied with an activating signal, said fourth common node being connected to a power supply terminal, and gates of said ninth and tenth transistors being supplied with a precharge signal before said activating signal.
Claim 4
Dependent Claim
37 words
The circuit as claimed in claim 1, wherein said eleventh transistor is connected between said second input/output terminal and said first transistor and said twelfth transistor is connected between said first input/output terminal and said second transistor.
Claim 5
Dependent Claim
35 words
The circuit as claimed in claim 1, wherein said eleventh transistor is connected between said first transistor and said reference terminal and said twelfth transistor is connected between said second transistor and said reference terminal.
Claim 6
Dependent Claim
54 words
The circuit as claimed in claim 1, wherein said first transistor is connected between said second input/output terminal and a circuit node and said second transistor is connected between said first input/output terminal and said circuit node, said eleventh and twelfth transistors being connected in series between said circuit node and said reference terminal.
Claim 7
Dependent Claim
299 words
A transistor circuit comprising a first input terminal supplied with an input signal voltage, a second input terminal supplied with a reference voltage, a first inverter having input and output terminals, a second inverter having input and output terminals connected respectively to said output and input terminals of said first inverter, a reference terminal, a first means coupled between said input terminal of said first inverter and said reference terminal and having a control terminal connected to said first input terminal for providing thereacross a first impedance representative of an amplitude of said input signal voltage, second means coupled between said input terminal of said second inverter and said reference terminal and having a control terminal connected to said second input terminal for providing thereacross a second impedance representative of an amplitude of said reference voltage, a third inverter having an input terminal, which is connected to said input terminal of said first inverter, and an output terminal, a fourth inverter having an input terminal, which is connected to said input terminal of said second inverter, and an output terminal, a first gate connected in series with said first means between said input terminal of said first inverter and said reference terminal and having a control terminal connected to said output terminal of said third inverter, a second gate connected in series with said second means between said input terminal of said second inverter and said reference terminal and having a control terminal connected to said output terminal of said fourth inverter, and third means coupled to said input terminals of said first and second inverters for producing an output signal having a first level when said first impedance is larger than said second impedance and a second level when said first impedance is smaller than said second impedance.
Claim 8
Dependent Claim
299 words
A transistor circuit comprising a first input terminal supplied with an input signal voltage, a second input terminal supplied with a reference voltage, a first inverter having input and output terminals, a second inverter having input and output terminals connected respectively to said output and input terminals of said first inverter, a reference terminal, a first means coupled between said input terminal of said first inverter and said reference terminal and having a control terminal connected to said first input terminal for providing thereacross a first impedance representative of an amplitude of said input signal voltage, second means coupled between said input terminal of said second inverter and said reference terminal and having a control terminal connected to said second input terminal for providing thereacross a second impedance representative of an amplitude of said reference voltage, a third inverter having an input terminal, which is connected to said input terminal of said first inverter, and an output terminal, a fourth inverter having an input terminal, which is connected to said input terminal of said second inverter, and an output terminal, a first gate connected in series with said first means between said input terminal of said first inverter and said reference terminal and having a control terminal connected to said output terminal of said third inverter, a second gate connected in series with said second means between said input terminal of said second inverter and said reference terminal and having a control terminal connected to said output terminal of said fourth inverter, and third means coupled to said input terminals of said first and second inverters for producing an output signal having a first level when said first impedance is larger than said second impedance and a second level when said first impedance is smaller than said second impedance.
Claim 9
Dependent Claim
26 words
The circuit as claimed in claim 6, wherein each of said first and second means and said first and second gates is composed of a transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-27 | 1994-02-26 | 1994-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-27 | 1998-02-26 | 1998-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-27 | 2002-02-26 | 2002-08-28 | $7700.00 | Window Closed / Lapsed |