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Patent US4952528A successfully refreshed from Google Patents.
US4952528A
Expired / Lapsed
US
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Photolithographic method for manufacturing semiconductor wiring patterns
Assignee: Toshiba Corp
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Filing: 1989-10-04
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Granted: 1990-08-28
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Expires: 2009-10-04
Abstract
Abstract A method for manufacturing semiconductor devices comprising the steps of forming a first wiring pattern including first and second lower layers on a semiconductor body, forming an insulation film which covers the first wiring pattern, forming a first hole of 1.5 μm and a second hole of 3 μm in first and second areas of the insulation film which lie over the first and second lower layers, forming a second wiring pattern having first and second upper layers respectively connected to the first and second lower layers via the first and second holes. In the method, the hole formation step includes the substeps of forming a resist film which covers the insulation film, forming a resist pattern by effecting the photolithographic process of exposing the insulation film to light by using a mask pattern having a first hole defining area of 1.5 μm and a second hole defining area of 2.4 μm, and etching the insulation film with the resist pattern used as a mask. The exposing light amount used in the resist pattern formation substep is previously determined so that the size of the first hole can be set equal to that of the first hole defining area, and the reduced amount of the second hole defining area is previously determined so that the size of the second hole obtained under the determined exposing light amount can be set to 3 μm.
Inventors
- 👤 Masahiro Abe
- 👤 Yasukazu Mase
- 👤 Toshihiko Katsura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:49
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H10W20/01; H10W20/071; H10W20/081; H10P; H10P50/00; H10P50/73; H10W20/092; Y; Y10; Y10S; Y10S148/00; Y10S148/137
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
270 words
A method for manufacturing semiconductor devices comprising the steps of: forming a first wiring pattern including at least first and second lower conductive layers formed on a semiconductor body; forming an insulation film which covers said first wiring pattern; forming a first contact hole of a first size and a second contact hole of a second size larger than the first size in first and second areas of said insulation film which lie over said first and second lower conductive layers; and forming a second wiring pattern having first and second upper conductive layers respectively connected to said first and second lower conductive layers via said first and second contact holes; wherein said contact hole formation step includes the sub-steps of forming a resist film which covers said insulation film; forming a resist pattern by effecting the photolithographic process of exposing said insulation film to light by using a mask pattern having a first contact hole defining area of a size substantially equal to the first size and a second contact hole defining area of a size smaller than the second size; and etching said insulation film with said resist pattern used as a mask; and the exposing light amount used in said resist pattern formation sub-step is previously determined so that the size of the first contact hole can be set equal to that of the first contact hole defining area, and the reduced amount of the second contact hole defining area is previously determined so that the size of the second contact hole obtained under the determined exposing light amount can be set equal to the second size.
Claim 2
Independent Claim
270 words
A method for manufacturing semiconductor devices comprising the steps of: forming a first wiring pattern including at least first and second lower conductive layers formed on a semiconductor body; forming an insulation film which covers said first wiring pattern; forming a first contact hole of a first size and a second contact hole of a second size larger than the first size in first and second areas of said insulation film which lie over said first and second lower conductive layers; and forming a second wiring pattern having first and second upper conductive layers respectively connected to said first and second lower conductive layers via said first and second contact holes; wherein said contact hole formation step includes the sub-steps of forming a resist film which covers said insulation film; forming a resist pattern by effecting the photolithographic process of exposing said insulation film to light by using a mask pattern having a first contact hole defining area of a size substantially equal to the first size and a second contact hole defining area of a size smaller than the second size; and etching said insulation film with said resist pattern used as a mask; and the exposing light amount used in said resist pattern formation sub-step is previously determined so that the size of the first contact hole can be set equal to that of the first contact hole defining area, and the reduced amount of the second contact hole defining area is previously determined so that the size of the second contact hole obtained under the determined exposing light amount can be set equal to the second size.
Claim 3
Dependent Claim
15 words
A method according to claim 1, wherein said first size is less than 3 μm.
Claim 4
Dependent Claim
31 words
A method according to claim 2, wherein said reduced amount of said second contact hole defining area is approximately 0.6 μm when said second size is not less than 3 μm.
Claim 5
Dependent Claim
41 words
A method according to claim 3, wherein the matching margin between said first contact hole and said first lower conductive layer and the matching margin between said second contact hole and said second lower conductive layer are set to 0.7 μm.
Claim 6
Dependent Claim
23 words
A method according to claim 1, wherein said semiconductor body includes a semiconductor substrate and an insulating film formed on said semiconductor substrate.
Claim 7
Dependent Claim
59 words
A method according to claim 5, wherein said semiconductor body further includes a plurality of semiconductor elements formed in the surface of said semiconductor substrate, an either said first or second lower conductive layer is connected to one of said semiconductor elements through an opening formed in said insulating layer and serving as an electrode for said semiconductor element.
Claim 8
Dependent Claim
15 words
A method according to claim 6, wherein said first wiring pattern is formed of aluminum.
References Cited (Backward Citations)
US4253888A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-27 | 1994-02-26 | 1994-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-27 | 1998-02-26 | 1998-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-27 | 2002-02-26 | 2002-08-28 | $7700.00 | Window Closed / Lapsed |