Charge-coupled device shift register

Claim 1

A shift register comprising four serial registers each having an input section for providing a sequence of charge samples, the four sequences of charge samples provided by the input sections of the four serial registers respectively being offset in phase relative to each other by 90° within the cycle of a clock signal, a transfer section, and a lead-in section disposed between the input section and the transfer section, and at least one of the serial registers comprising: at least first lead-in gate means and second lead-in gate means over the lead-in section, the second lead-in gate means being between the first lead-in gate means and the transfer section, and means for driving the first lead-in gate means and the second lead-in gate means each at the frequency of the clock signal, the drive signal applied to the second lead-in gate means being retarded in phase relative to that applied to the first lead-in gate means by 90° within the cycle of the clock signal. wherein a first serial register comprises first lead-in gate means, a second serial register and a third serial register each comprise first lead-in gate means and second lead-in gate means, and a fourth serial register comprises first lead-in gage means, second lead-in gate means and third lead-in gate means.