Method and apparatus for measuring the quality of digital signals

Claim 2

Method of measuring the quality of a digital signal comprising data words and reproduced from a magnetic tape by an equipment having an error recognition circuit for tagging a signal portion containing an error with an error flag and error processing circuits for correcting correctable errors, concealing uncorrectable errors and identifying kinds of errors, and also having at least one binary number register used in registering the summing of errors detected by said error recognition circuit, said method comprising the steps of: pre-setting the duration of intervals to be used successively for error occurrence information; measuring the number of at least one kind of errors recognized in each of successive intervals of said pre-set duration and averaging the numbers so measured over a predetermined number of said intervals; changing the presetting of the duration of said intervals in the event the average number of errors per interval is less than 1 or approximates the number corresponding to overflow of said at least one register, for maintaining said average number within the range of said at least one register.

Claim 3

Method according to claim 1, wherein said equipment includes means for identifying an error pattern by the rate of occurrence of detected errors in a predetermined number (n) of successive signal portions of equal length, wherein said method includes the step of selecting for measurement the rate of occurrences of a selected one of the following: correctable errors, uncorrectable errors, single bit errors in respective signal portions which are error-protected by check words, and a particular level of multiple bit errors in said respective signal portions.

Claim 4

Method of measuring the quality of digital signals comprising data word blocks which respectively include check words for detecting and correcting errors, which is reproduced from magnetic tape by an equipment having error recognition, correction and concealment circuits, said method comprising the steps of: pre-setting a number for an initial count of block end signals. producing a block end signal (BE) at the end of every said block, and counting said block signals; in response to each said block end signal, adding a number representing errors detected in said block to a previous error sum, if any, stored in a register (and in the absence of a previously stored sum adding said number to zero) and then writing the resulting sum in said register; in response to the counting of said block end signals reaching said preset number, resetting the counting of block end signals and dividing by 2 the sum produced by adding said number representing detected errors to a previous sum in said register before the resulting sum is written into said register, and changing said preset number in response to the magnitude of said sum resulting when the counting of said block end signals reaches said preset number to an extent suitable for keeping the content of said register from overflowing while favoring the rise of said content into a midportion of the range of values storable in said register.

Claim 5

Method of measuring the quality of digital signals comprising data word blocks which respectively include check words for detecting and correcting errors, which is reproduced from magnetic tape by an equipment having error recognition, correction and concealment circuits, said method comprising the steps of: pre-setting a number for an initial count of block end signals. producing a block end signal (BE) at the end of every said block, and counting said block signals; in response to each said block end signal, adding a number representing errors detected in said block to a previous error sum, if any, stored in a register (and in the absence of a previously stored sum adding said number to zero) and then writing the resulting sum in said register; in response to the counting of said block end signals reaching said preset number, resetting the counting of block end signals and dividing by 2 the sum produced by adding said number representing detected errors to a previous sum in said register before the resulting sum is written into said register, and changing said preset number in response to the magnitude of said sum resulting when the counting of said block end signals reaches said preset number to an extent suitable for keeping the content of said register from overflowing while favoring the rise of said content into a midportion of the range of values storable in said register.

Claim 6

Method according to claim 3, wherein after said preset number is found to favor the rise of the content of said register into a high midportion of the said range, said step of dividing by 2 the addition result of an error count and a sum previously stored in said register before writing the resulting sum into said register is performed in response to the occurrence of every block end signal (BE).

Claim 7

Method of optimizing the operation of an equipment for reproducing a digital signal from a magnetic tape, said equipment having an error recognition circuit for tagging a signal portion containing an error with an error flag and also having at least one binary number register for use in registering the summing of error flags produced by the error recognition circuit, said method comprising the steps of: re-setting the duration of intervals to be used successively for error occurrence information; measuring the number of at least one kind of errors recognized in each of successive intervals of preset duration and averaging the number so measured over a predetermined number of said intervals; changing the presetting of the duration of said intervals in the event the average number of errors in a said interval is less than 1 or approximates a number corresponding to overflow of said at least one register, for maintaining said average number within the range of said at least one register; and adjusting an operating parameter of said equipment for the purpose of optimizing adjustment of said operating parameter and then repeating the measurement of the number of at least one kind of errors recognized in each of successive intervals and averaging the number so measured over a predetermined number of said intervals, followed by further sequences of said adjustments and measurement/averaging steps, to determine an optimal adjustment of said parameter for which the average of numbers of errors so measured is at least approximately a minimum.

Claim 8

Method of optimizing the operation of an equipment for reproducing a digital signal from a magnetic tape, said equipment having an error recognition circuit for tagging a signal portion containing an error with an error flag and also having at least one binary number register for use in registering the summing of error flags produced by the error recognition circuit, said method comprising the steps of: re-setting the duration of intervals to be used successively for error occurrence information; measuring the number of at least one kind of errors recognized in each of successive intervals of preset duration and averaging the number so measured over a predetermined number of said intervals; changing the presetting of the duration of said intervals in the event the average number of errors in a said interval is less than 1 or approximates a number corresponding to overflow of said at least one register, for maintaining said average number within the range of said at least one register; and adjusting an operating parameter of said equipment for the purpose of optimizing adjustment of said operating parameter and then repeating the measurement of the number of at least one kind of errors recognized in each of successive intervals and averaging the number so measured over a predetermined number of said intervals, followed by further sequences of said adjustments and measurement/averaging steps, to determine an optimal adjustment of said parameter for which the average of numbers of errors so measured is at least approximately a minimum.

Claim 9

Method according to claim 5, wherein said adjustments are made for optimizing the tracking of the path of magnetic heads used for scanning magnetic tape with oblique tracks on said tape on which said digital signal is recorded.

Claim 10

Method according to claim 6, wherein a microcomputer is used having a stored program for varying tracking adjustment and measuring magnitude of change and the direction of change of the error rate and, in response to changes in the error rate, correcting the tracking adjustment.

Claim 11

Method according to claim 5, wherein the operating parameter of said equipment which is to be adjusted is a transfer characteristic of a distortion compensator having an adjustable transfer characteristic, whereby said transfer characteristic is optimized so as to produce a minimum in the measured error rate.

Claim 12

Method according to claim 8, wherein the error rate measured is the rate of occurrence of single bit errors in portions of a digital signal having a predetermined length, disregarding the occurrence of multiple bit errors occurring in data signal portions of said predetermined length.

Claim 13

Apparatus for measuring the quality of a digital signal comprising data words and reproduced from a magnetic tape by an equipment having an error recognition circuit for tagging a signal portion containing an error with an error flag and error processing circuits for correcting correctable errors, concealing uncorrectable errors and identifying kinds of errors, said apparatus further comprising: an error selection circuit (8) for selecting at least one kind of error for measurement of the occurrence thereof, connected to said error recognition and processing circuits for receiving information on the occurrence of a plurality of kinds of errors and having a selection control circuit (21) for selecting at least one kind of errors for designating at an output of said selection circuit (8); means for obtaining block end signals from said error recognition and processing circuits designating the end of each said digital signal portion capable of being tagged with an error flag; a first register (9) for registering error information relating to each said digital signal portion under control of said error selection circuit (8), said first register being clocked by said block end signals for being cleared and for transferring its content in response to each block end signal, said content being transferred by an output of said first register; a second register (10) and an adding circuit (11), said adding circuit being connected for adding the output of said first register to the output of said second register and having an output; a controllable multi-bit changeover switch (12) having an input connected to the output of said addition circuit and an output connected to an input of said second register, said changeover switch being connected and controllable for providing to its output either the content of its input, or that content divided by 2 by virtue of a one-place shift towards the least significant bit, and means for controlling said switch in accordance with a settable variable number of said block end signals and thereby making it likely that the contents of said second register (10) will be in a mid range of its capacity for binary numbers.

Claim 14

Apparatus for measuring the quality of a digital signal comprising data words and reproduced from a magnetic tape by an equipment having an error recognition circuit for tagging a signal portion containing an error with an error flag and error processing circuits for correcting correctable errors, concealing uncorrectable errors and identifying kinds of errors, said apparatus further comprising: an error selection circuit (8) for selecting at least one kind of error for measurement of the occurrence thereof, connected to said error recognition and processing circuits for receiving information on the occurrence of a plurality of kinds of errors and having a selection control circuit (21) for selecting at least one kind of errors for designating at an output of said selection circuit (8); means for obtaining block end signals from said error recognition and processing circuits designating the end of each said digital signal portion capable of being tagged with an error flag; a first register (9) for registering error information relating to each said digital signal portion under control of said error selection circuit (8), said first register being clocked by said block end signals for being cleared and for transferring its content in response to each block end signal, said content being transferred by an output of said first register; a second register (10) and an adding circuit (11), said adding circuit being connected for adding the output of said first register to the output of said second register and having an output; a controllable multi-bit changeover switch (12) having an input connected to the output of said addition circuit and an output connected to an input of said second register, said changeover switch being connected and controllable for providing to its output either the content of its input, or that content divided by 2 by virtue of a one-place shift towards the least significant bit, and means for controlling said switch in accordance with a settable variable number of said block end signals and thereby making it likely that the contents of said second register (10) will be in a mid range of its capacity for binary numbers.

Claim 15

Apparatus according to claim 10, wherein said means for controlling said switch comprise a counter connected for counting said block end signals and means (14) for setting said counter to count out a particular number of said block end signals to produce an output signal for controlling said switch (12) to produce division by two during the interval following each counting out operation which ends not later than the next block end signal.

Claim 16

Apparatus according to claim 11, wherein a third register (15) is provided having its input connected to an output of said second register (10) for transfer of content from said second register to said third register, said third register being arranged to be clocked for loading of content at substantially the same intervals at which said switch (12) is operated by said counter (13), and also a memory unit (17) having an input connected to the output of said third register and containing tabular stored information for evaluation of information obtained from said third register 15 and furnishing it for controlling said means (14) for setting the count length of said counter (13), said output of said memory 17, being also furnished to an output of the above defined apparatus.

Claim 17

Apparatus according to claim 10, wherein said selection circuit (8)comprises a programmable read only memory (PROM).