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US4951257A
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Reference setting circuit for determining written-in content in nonvolatile semiconductor memories
Assignee: Toshiba Corp
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Filing: 1988-05-23
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Granted: 1990-08-21
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Expires: 2008-05-23
Abstract
Abstract A nonvolatile semiconductor memory according to this invention is so constructed that different data readout references are used in an ordinary readout mode and in a program verification mode. The different read-out references can be set by changing reference input potential VREF supplied to a differential sense amplifier for amplifying a potential derived onto a bit line from a memory cell, or by changing an input threshold level of a circuit for sensing the potential on the bit line. In this case, the readout reference in the program verification mode is set severe, or high, in comparison with that in the ordinary readout mode.
Inventors
- 👤 Keniti Imamiya
- 👤 Sumio Tanaka
- 👤 Junichi Miyamoto
- 👤 Shigeru Atsumi
- 👤 Yumiko Iyama
- 👤 Nobuaki Ohtsuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 01:11
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
101 words
A reference setting circuit for determining written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and a program verification mode in which the contents written in said memory cell means are verified; and data readout means, connected to said memory cell means, for reading data from the memory cell means, and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode.
Claim 2
Dependent Claim
101 words
A reference setting circuit for determining written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and a program verification mode in which the contents written in said memory cell means are verified; and data readout means, connected to said memory cell means, for reading data from the memory cell means, and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode.
Claim 3
Dependent Claim
94 words
A circuit according to claim 1, wherein said data readout means includes sense amplifier means for comparing a bit line potential at a bit line of said memory cell means and the reference potential, to read out data from said memory cell means; and wherein said reference changing means includes reference potential generating means, connected to said sense amplifier means, for generating the reference potential; and potential changing means, connected to said reference potential generating means, for changing the reference potential according to whether the program verification mode or ordinary readout mode is active.
Claim 4
Dependent Claim
81 words
A circuit according to claim 1, wherein said data readout means includes sense amplifier means for detecting a bit line potential at a bit line of said memory cell means by use of a predetermined input threshold value, thereby reading out data from said memory cell means; and said reference changing means includes threshold changing means connected to said sense amplifier means, for changing the input threshold value according to whether the program verification mode or ordinary readout mode is active.
Claim 5
Dependent Claim
127 words
A reference setting circuit for determining the written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and in a program verification mode in which the contents written in said memory cell means are verified; sense amplifier means for comparing a bit line potential at a bit line of said memory cell means and a reference potential, to read out data from said memory cell means; and a dummy cell means, connected to said sense amplifier means, and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode.
Claim 6
Dependent Claim
127 words
A reference setting circuit for determining the written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and in a program verification mode in which the contents written in said memory cell means are verified; sense amplifier means for comparing a bit line potential at a bit line of said memory cell means and a reference potential, to read out data from said memory cell means; and a dummy cell means, connected to said sense amplifier means, and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode.
Claim 7
Dependent Claim
288 words
A reference setting circuit for determining the written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and in a program verification mode in which the contents written in said memory cell means are verified; sense amplifier means for comparing a bit line potential at a bit line of said memory cell means and a reference potential, to read out data from said memory cell means; and a dummy cell means connected to said sense amplifier means and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode in which the contents written in said memory cell means are verified, the reference changing means including: variable potential generating means for generating a reference potential selection signal that is set to a first logic level in the program verification mode and to a second logic level in the ordinary readout mode; a first MOS transistor, having a source connected to a first circuit kept at a potential corresponding to the first logic level and a gate connected to receive the reference potential selection signal; a second MOS transistor, connected to said sense amplifier means and connected between a circuit to which is applied the reference potential and to a second circuit kept at a potential corresponding to the second logic level; and a third MOS transistor; having a gate that is set at a preset bias potential and a drain-source path connected between the circuit, to which is applied the reference potential, and a drain of said first MOS transistor.
Claim 8
Dependent Claim
288 words
A reference setting circuit for determining the written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and in a program verification mode in which the contents written in said memory cell means are verified; sense amplifier means for comparing a bit line potential at a bit line of said memory cell means and a reference potential, to read out data from said memory cell means; and a dummy cell means connected to said sense amplifier means and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode in which the contents written in said memory cell means are verified, the reference changing means including: variable potential generating means for generating a reference potential selection signal that is set to a first logic level in the program verification mode and to a second logic level in the ordinary readout mode; a first MOS transistor, having a source connected to a first circuit kept at a potential corresponding to the first logic level and a gate connected to receive the reference potential selection signal; a second MOS transistor, connected to said sense amplifier means and connected between a circuit to which is applied the reference potential and to a second circuit kept at a potential corresponding to the second logic level; and a third MOS transistor; having a gate that is set at a preset bias potential and a drain-source path connected between the circuit, to which is applied the reference potential, and a drain of said first MOS transistor.
Claim 9
Dependent Claim
316 words
A reference setting circuit for determining the written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and in a program verification mode in which the contents written in said memory cell means are verified; sense amplifier means for comparing a bit line potential at a bit line of said memory cell means and a reference potential, to read out data from said memory cell means; and a dummy cell means connected to said sense amplifier means and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode in which the contents written in said memory cell means are verified, the reference changing means including: variable potential generating means for generating a reference potential selection signal that is set to a first logic level in the program verification mode and to a second logic level in the ordinary readout mode; a first MOS transistor, having a source connected to a first circuit kept at a potential corresponding to the first logic level and a gate set at a potential corresponding to the second logic level; a second MOS transistor, having a source connected to the drain of said first MOS transistor and a gate connected to receive the reference potential selection signal; a third MOS transistor, connected to said sense amplifier means and connected between a circuit, to which is applied the reference potential, and a second circuit kept at a potential corresponding to the second logic level; and a fourth MOS transistor, having a gate that is set at a preset bias potential and a drain-source path connected between the circuit, to which is applied the reference potential, and the drain of said second MOS transistor.
Claim 10
Dependent Claim
316 words
A reference setting circuit for determining the written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and in a program verification mode in which the contents written in said memory cell means are verified; sense amplifier means for comparing a bit line potential at a bit line of said memory cell means and a reference potential, to read out data from said memory cell means; and a dummy cell means connected to said sense amplifier means and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode in which the contents written in said memory cell means are verified, the reference changing means including: variable potential generating means for generating a reference potential selection signal that is set to a first logic level in the program verification mode and to a second logic level in the ordinary readout mode; a first MOS transistor, having a source connected to a first circuit kept at a potential corresponding to the first logic level and a gate set at a potential corresponding to the second logic level; a second MOS transistor, having a source connected to the drain of said first MOS transistor and a gate connected to receive the reference potential selection signal; a third MOS transistor, connected to said sense amplifier means and connected between a circuit, to which is applied the reference potential, and a second circuit kept at a potential corresponding to the second logic level; and a fourth MOS transistor, having a gate that is set at a preset bias potential and a drain-source path connected between the circuit, to which is applied the reference potential, and the drain of said second MOS transistor.
Claim 11
Dependent Claim
357 words
A reference setting circuit for determining the written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and in a program verification mode in which the contents written in said memory cell means are verified; sense amplifier means for comparing a bit line potential at a bit line of said memory cell means and a reference potential, to read out data from said memory cell means; and a dummy cell means connected to said sense amplifier means and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode in which the contents written in said memory cell means are verified, the reference changing means including: variable potential generating means for generating a reference potential selection signal that is set to a first logic level in the program verification mode and to a second logic level in the ordinary readout mode; a first MOS transistor, having a source connected to a first circuit kept at a potential corresponding to the first logic level and a gate set at a potential corresponding to the second logic level; a second MOS transistor, having a source connected to the drain of said first MOS transistor and a gate set at a potential corresponding to the second logic level; a third MOS transistor, having a gate set at a preset bias potential and a drain-source path connected between the circuit that is to have the reference potential applied thereto, and the drain of said second MOS transistor; a first transistor circuit, connected to said sense amplifier means and connected between a circuit that is to have the reference potential applied thereto, and a second circuit kept at a potential corresponding to the second logic level; and a second transistor circuit, connected to the circuit to which the reference potential is applied and to said second circuit, for changing the reference potential in accordance with the logic level of the reference potential selection signal.
Claim 12
Dependent Claim
357 words
A reference setting circuit for determining the written-in contents of a nonvolatile semiconductor memory, comprising: a memory cell means for storing data of the nonvolatile semiconductor memory, said memory cell means operable in an ordinary readout mode and in a program verification mode in which the contents written in said memory cell means are verified; sense amplifier means for comparing a bit line potential at a bit line of said memory cell means and a reference potential, to read out data from said memory cell means; and a dummy cell means connected to said sense amplifier means and including reference changing means, connected to the memory cell means, for setting different references used for determining data in the ordinary readout mode and in the program verification mode in which the contents written in said memory cell means are verified, the reference changing means including: variable potential generating means for generating a reference potential selection signal that is set to a first logic level in the program verification mode and to a second logic level in the ordinary readout mode; a first MOS transistor, having a source connected to a first circuit kept at a potential corresponding to the first logic level and a gate set at a potential corresponding to the second logic level; a second MOS transistor, having a source connected to the drain of said first MOS transistor and a gate set at a potential corresponding to the second logic level; a third MOS transistor, having a gate set at a preset bias potential and a drain-source path connected between the circuit that is to have the reference potential applied thereto, and the drain of said second MOS transistor; a first transistor circuit, connected to said sense amplifier means and connected between a circuit that is to have the reference potential applied thereto, and a second circuit kept at a potential corresponding to the second logic level; and a second transistor circuit, connected to the circuit to which the reference potential is applied and to said second circuit, for changing the reference potential in accordance with the logic level of the reference potential selection signal.
References Cited (Backward Citations)
US4223394A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-20 | 1994-02-19 | 1994-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-20 | 1998-02-19 | 1998-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-20 | 2002-02-19 | 2002-08-21 | $7700.00 | Window Closed / Lapsed |