Patent US4951252A successfully refreshed from Google Patents.
US4951252A
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Digital memory system
Assignee: Texas Instruments Inc
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Filing: 1988-10-25
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Granted: 1990-08-21
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Expires: 2008-10-25
Abstract
Abstract A digital memory system of the type which includes an amplifier transistor connected to provide an amplified bit line signal corresponding to the state of a selected memory cell. A bit line pull-up transistor is positioned to function as a bit line current source and as a load device for the amplifier transistor. The amplifier transistor is connected between the pull-up transistor and the bit line and an output node positioned between the pull-up and amplifier transistors provides the amplified bit line signal corresponding to the state of a selected memory cell.
Inventors
- 👤 William A. White
- 👤 Albert H. Taddiken
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:22
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/12
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
147 words
A digital memory system comprising: at least one column of memory cells; a plurality of word lines connected for selecting a memory cell; a first bit line connected to each memory cell in the column for determining the state of a selected cell; a bit line pull-up transistor having first, second and third terminals, the first terminal connectable to a source of power and the third terminal connected to form a current source at the second terminal; an amplifier transistor having first and second source/drain electrodes and a gate electrode, the first source/drain electrode connected to the second terminal of the pull-up transistor, the second source/drain electrode connected to the bit line and the gate electrode connected to receive a bias voltage; and an output node between the pull-up and amplifier transistors providing an amplified bit line signal corresponding to the state of a selected memory cell.
Claim 2
Dependent Claim
147 words
A digital memory system comprising: at least one column of memory cells; a plurality of word lines connected for selecting a memory cell; a first bit line connected to each memory cell in the column for determining the state of a selected cell; a bit line pull-up transistor having first, second and third terminals, the first terminal connectable to a source of power and the third terminal connected to form a current source at the second terminal; an amplifier transistor having first and second source/drain electrodes and a gate electrode, the first source/drain electrode connected to the second terminal of the pull-up transistor, the second source/drain electrode connected to the bit line and the gate electrode connected to receive a bias voltage; and an output node between the pull-up and amplifier transistors providing an amplified bit line signal corresponding to the state of a selected memory cell.
Claim 3
Dependent Claim
22 words
The system of claim 1 wherein the pull-up transistor is a field effect transistor and the third terminal is a gate electrode.
Claim 4
Dependent Claim
36 words
The system of claim 1 wherein the pull-up transistor is a field effect transistor with the first and second terminals being source/drain electrodes and the third terminal being a gate electrode connected to the second terminal.
Claim 5
Dependent Claim
134 words
The system of claim 1 further including: a second bit line also connected to each memory cell in the column; a second bit line pull-up transistor having first, second and third terminals, the first terminal connectable to the source of power and the third terminal connected to form a current source at the second terminal; a second amplifier transistor having first and second source/drain electrodes and a gate electrode, the first source/drain electrode connected to the second terminal of the second pull-up transistor, the second source/drain electrode connected to the second bit line and the gate electrode connected to receive a bias voltage; and a second output node between the second pull-up transistor and the second amplifier transistor providing an amplified bit line signal corresponding to the inverted state of a selected memory cell.
Claim 6
Dependent Claim
74 words
The system of claim 4 wherein: the gate electrode of the first amplifier transistor is connected to the second source/drain electrode of the second amplifier transistor; and the gate electrode of the second amplifier transistor is connected to the second source/drain electrode of the first amplifier transistor said connections providing gate to source voltages in proportion to the difference between voltage levels of the first and second bit lines relative to a reference potential.
Claim 7
Dependent Claim
40 words
The system of claim 5 wherein the first and second pull-up transistors each are a field effect transistor with the first and second terminals being source/drain electrodes and the third terminal being a gate electrode connected to the second terminal.
Claim 8
Dependent Claim
16 words
The system of claim 4 wherein the pull-up transistors and the amplifier transistors are GaAs MESFETs.
Claim 9
Dependent Claim
32 words
The system of claim 1 wherein the bit line includes a terminal connectable to a reference potential, said system further including a diode serially connected between the terminal and the reference potential.
Claim 10
Dependent Claim
17 words
The system of claim 1 wherein the pull up transistors and the amplifier transistor are GaAs MESFETs.
Claim 11
Dependent Claim
121 words
A digital memory system comprising: at least a first column of memory cells; a plurality of word lines connected for selecting a memory cell; a plurality of word lines connected for selecting a memory cell; a first bit line connected to each memory cell in the column for determining the state of a selected cell; an amplifier transistor connected to provide an amplified bit line signal corresponding to the state of a selected memory cell; and a bit line pull-up transistor connectable to a source of power and positioned to function as a current source for the bit line and as a load device for the amplifier transistor, said amplifier transistor positioned between said pull-up transistor and said first bit line.
Claim 12
Dependent Claim
121 words
A digital memory system comprising: at least a first column of memory cells; a plurality of word lines connected for selecting a memory cell; a plurality of word lines connected for selecting a memory cell; a first bit line connected to each memory cell in the column for determining the state of a selected cell; an amplifier transistor connected to provide an amplified bit line signal corresponding to the state of a selected memory cell; and a bit line pull-up transistor connectable to a source of power and positioned to function as a current source for the bit line and as a load device for the amplifier transistor, said amplifier transistor positioned between said pull-up transistor and said first bit line.
Claim 13
Dependent Claim
17 words
The digital memory system according to claim 10 wherein said system is a static random access memory.
Claim 14
Dependent Claim
80 words
In a static random access memory device including at least a first column of memory cells, a plurality of word lines and bit lines connected for memory cell selection, a pull-up device and an amplifier transistor coupled to a first bit line, a method for enhancing high speed operation comprising the step of isolating the capacitance of a bit line from the associated bit line pull-up device by positioning the amplifier transistor between the pull-up device and the bit line.
Claim 15
Dependent Claim
80 words
In a static random access memory device including at least a first column of memory cells, a plurality of word lines and bit lines connected for memory cell selection, a pull-up device and an amplifier transistor coupled to a first bit line, a method for enhancing high speed operation comprising the step of isolating the capacitance of a bit line from the associated bit line pull-up device by positioning the amplifier transistor between the pull-up device and the bit line.
Claim 16
Dependent Claim
35 words
The method of claim 12 wherein the step of isolating the bit line capacitance further includes positioning the pull-up device to function as the amplifier transistor load as well as the bit line current source.
Claim 17
Dependent Claim
80 words
The method of claim 12 wherein the bit line amplifier transistor is an FET and the device includes a second bit line connected to the first column for memory cell selection, a second pull-up device and a second amplifier transistor coupled to the second bit line, the method further comprising the step of coupling the gate of the first amplifier transistor to the second bit line and coupling the gate of the second amplifier transistor to the first bit line.
References Cited (Backward Citations)
US4665508A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-20 | 1994-02-19 | 1994-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-20 | 1998-02-19 | 1998-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-20 | 2002-02-19 | 2002-08-21 | $7700.00 | Window Closed / Lapsed |