US4951238A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor for executing arithmetic operations on input data and constant data with a small error
Assignee: NEC Corp
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Filing: 1987-10-30
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Granted: 1990-08-21
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Expires: 2007-10-30
Abstract
Abstract A process for carrying out modulo reduction of floating-point data uses a predetermined constant. A subtraction operation of more significant bits of the predetermined constant from a mantissa part of the floating-point data is performed and the subtraction result is normalized. Less significant bits of the predetermined constant are shifted and this result is subtracted from the above normalized data and is then normalized. Thus, a remainder resulting from the modulo reduction is obtained.
Inventors
- 👤 Misayo Sasahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:38
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/485; G06F7/544; G06F7/5446; G06F7/548; G06F7/60; G06F7/72; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3812; G06F2207/382; G06F7/499; G06F7/49936
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
112 words
A processor comprising: memory means for storing more significant bits and less significant bits of a particular constant, first arithmetic means for carrying out a subtraction operation of said more significant bits from input data to produce first data, first normalizing means for normalizing said first data to produce second data, shift means for shifting said less significant bits to align a digit of a most significant bit of said less significant bits to a corresponding digit of said second data, second arithmetic means for carrying out a subtraction operation of shifted less significant bits from said second data to produce third data, and second normalizing means for normalizing said third data.
Claim 2
Dependent Claim
112 words
A processor comprising: memory means for storing more significant bits and less significant bits of a particular constant, first arithmetic means for carrying out a subtraction operation of said more significant bits from input data to produce first data, first normalizing means for normalizing said first data to produce second data, shift means for shifting said less significant bits to align a digit of a most significant bit of said less significant bits to a corresponding digit of said second data, second arithmetic means for carrying out a subtraction operation of shifted less significant bits from said second data to produce third data, and second normalizing means for normalizing said third data.
Claim 3
Dependent Claim
41 words
A processor as claimed in claim 1, wherein said memory means stores said more significant bits at a first memory location having a first memory address and said less significant bits at a second memory location having a second memory address.
Claim 4
Dependent Claim
33 words
A processor as claimed in claim 1, wherein a mantissa part of said particular constant has a bit length that is twice a bit length of a mantissa part of said input data.
Claim 5
Dependent Claim
214 words
A processor for carrying out modulo reduction of input data by the use of a predetermined constant, said processor comprising: first means for storing more significant bits and less significant bits of a mantissa part of said predetermined constant, each of said more significant bits and said less significant bits having a bit length equal to a bit length of a mantissa part of said input data, second means for subtracting said more significant bits from data corresponding to said mantissa part of said input data to produce first data, third means for detecting a bit position of a leading-1 of said first data to produce first shift-data, fourth means for shifting said first data by a number of bits specified by said first shift-data to produce second data, fifth means for shifting said less significant bits by said number of bits specified by said first shift-data and said bit length of said mantissa part of said input data to produce third data, sixth means for subtracting said third data from said second data to produce fourth data, detecting means for detecting a bit position of a leading-1 of said fourth data to produce second shift-data, and seventh means for shifting said fourth data by a number of bits specified by said second shift-data.
Claim 6
Dependent Claim
214 words
A processor for carrying out modulo reduction of input data by the use of a predetermined constant, said processor comprising: first means for storing more significant bits and less significant bits of a mantissa part of said predetermined constant, each of said more significant bits and said less significant bits having a bit length equal to a bit length of a mantissa part of said input data, second means for subtracting said more significant bits from data corresponding to said mantissa part of said input data to produce first data, third means for detecting a bit position of a leading-1 of said first data to produce first shift-data, fourth means for shifting said first data by a number of bits specified by said first shift-data to produce second data, fifth means for shifting said less significant bits by said number of bits specified by said first shift-data and said bit length of said mantissa part of said input data to produce third data, sixth means for subtracting said third data from said second data to produce fourth data, detecting means for detecting a bit position of a leading-1 of said fourth data to produce second shift-data, and seventh means for shifting said fourth data by a number of bits specified by said second shift-data.
Claim 7
Dependent Claim
37 words
A processor as claimed in claim 4, wherein said fourth and seventh means respectively shift said first and fourth data in a leftward direction, and said fifth means shifts said less significant bits in a rightward direction.
Claim 8
Dependent Claim
126 words
A processor comprising: memory means for storing more significant bits and less significant bits of a predetermined constant at first and second addresses, respectively, first arithmetic means for subtracting said more significant bits from input data to produce first data, first shift means for shifting said first data until a most significant bit of said first data changes to 1 to produce second data, second shift means for shifting said less significant bits in a direction opposite to a data-shifting direction of said first data to produce third data, second arithmetic means for subtracting said third data from said second data to produce fourth data, and third shift means for shifting said fourth data until a most significant bit of said fourth data changes to 1.
Claim 9
Dependent Claim
126 words
A processor comprising: memory means for storing more significant bits and less significant bits of a predetermined constant at first and second addresses, respectively, first arithmetic means for subtracting said more significant bits from input data to produce first data, first shift means for shifting said first data until a most significant bit of said first data changes to 1 to produce second data, second shift means for shifting said less significant bits in a direction opposite to a data-shifting direction of said first data to produce third data, second arithmetic means for subtracting said third data from said second data to produce fourth data, and third shift means for shifting said fourth data until a most significant bit of said fourth data changes to 1.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-20 | 1994-02-19 | 1994-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-20 | 1998-02-19 | 1998-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-20 | 2002-02-19 | 2002-08-21 | $7700.00 | Window Closed / Lapsed |