Synchronizing circuit for offset quaternary phase shift keying

Claim 1

A synchronizing circuit for offset quaternary phase shift keying, comprising: a four-phase demodulator for providing a demodulated signal sample x k sampled at bit time k and having a real component x k c and an imaginary component x k s ; a processing module responsive to the real and imaginary components of the output of the four-phase demodulator for deriving from each signal sample x k a corresponding useful sample y k c on a real path and a corresponding synchronization sample y k s on an imaginary path, and deriving from each useful sample x k a corresponding decision variable d k equal to the sign of the useful sample y k c ; a phase error calculating circuit responsive to the output of the processing module for deriving a phase loop error correction signal g1(d k-2 -d k )y k-1 c +d k-1 ·y k-1 s where y k-1 c is y k c shifted by one bit period, y k-1 s is y k s shifted by one bit period, d k-2 is d k shifted by two bit periods, d k-1 is d k shifted by one bit period, g1=g(T), T is the bit period, and g(t) is the overall impulse response of the filtering to which the signal is subjected; and a phase correcting circuit responsive to the phase loop error correction signal for changing the phase of the useful sample.