Apparatus and method for converting floating point data formats in a microprocessor

Claim 2

In a computer system which includes a two-phase clocking means, a data format conversion apparatus for converting floating point data formats comprising: decoding means for decoding an instruction in response to a first phase of a first clock pulse to begin the conversion of a floating point number having a first kind of format and for providing signal when said instruction is received; constant generating means for providing a certain constant prior to the end of a second phase of said first clock pulse in response to said first signal; latching means or latching said floating point number in aid first kind of format and said certain constant; and adder means for adding said certain constant to said floating point number of said first kind of format to produce a result which is said floating point number in a second kind of format.

Claim 3

The apparatus of claim 1 further comprising a register means for receiving and storing said result in response to a second phase of a second clock pulse.

Claim 4

A computer system including a CPU, a two-phase clocking means providing a first phase and a second phase clock signal, a floating point unit capable of performing floating point arithmetic operations, and a floating point data conversion apparatus for converting the exponent portion of a biased floating point number having a first format to a second format, said conversion apparatus comprising: decoding means for receiving and decoding a microcode instruction, said decoding means providing a first signal in response to a certain microcode instruction which indicates that a conversion is to be performed; a first transmission means for coupling said microcode instruction to said decoding means in response to a first phase of a first clock pulse; control means for receiving said first signal and for producing a second signal in response to said first signal; memory means for storing a plurality of constants and for producing a certain constant from one of said plurality of constants in response to said second signal; a second transmission means for coupling said first signal to said control means in response to a second phase of said first clock signal, said certain constant being produced by said memory means prior to the end of said second phase; adder means for adding said exponent portion of said floating point number in said first format to said certain constant, said adder means producing a result which represents said exponent portion of said floating point number in said second format.

Claim 5

A computer system including a CPU, a two-phase clocking means providing a first phase and a second phase clock signal, a floating point unit capable of performing floating point arithmetic operations, and a floating point data conversion apparatus for converting the exponent portion of a biased floating point number having a first format to a second format, said conversion apparatus comprising: decoding means for receiving and decoding a microcode instruction, said decoding means providing a first signal in response to a certain microcode instruction which indicates that a conversion is to be performed; a first transmission means for coupling said microcode instruction to said decoding means in response to a first phase of a first clock pulse; control means for receiving said first signal and for producing a second signal in response to said first signal; memory means for storing a plurality of constants and for producing a certain constant from one of said plurality of constants in response to said second signal; a second transmission means for coupling said first signal to said control means in response to a second phase of said first clock signal, said certain constant being produced by said memory means prior to the end of said second phase; adder means for adding said exponent portion of said floating point number in said first format to said certain constant, said adder means producing a result which represents said exponent portion of said floating point number in said second format.

Claim 6

The computer system of claim 3 wherein said apparatus further compirses a register means for receiving and storing said result in response to a second phase of said second clock pulse.

Claim 7

The computer system of claim 4 wherein said memory means comprises a read-only memory.

Claim 8

The computer system of claim 5 wherein said floating point number in said first format comprises either a single precision real, double precision real, or an extended precision real floating point number.

Claim 9

In a computer system which includes a two-phase clocking means and a floating point unit, a method of converting the exponent portion of a biased floating point number from a first format to a second format comprising the steps of: decoding a microcode instruction calling for the conversion of said number from said first format to said second format in response to a first phase of a first clock pulse; selecting a certain constant from a read-only memory prior to the end of said second phase of said first clock pulse; adding said certain constant and said floating point number in said first format to obtain a result which is said exponent of said floating point number in said second format; storing said result in an exponent register in response to a second phase of a second clock pulse.

Claim 10

In a computer system which includes a two-phase clocking means and a floating point unit, a method of converting the exponent portion of a biased floating point number from a first format to a second format comprising the steps of: decoding a microcode instruction calling for the conversion of said number from said first format to said second format in response to a first phase of a first clock pulse; selecting a certain constant from a read-only memory prior to the end of said second phase of said first clock pulse; adding said certain constant and said floating point number in said first format to obtain a result which is said exponent of said floating point number in said second format; storing said result in an exponent register in response to a second phase of a second clock pulse.

Claim 11

The method of claim 7 further including the step of latching said certain constant and said floating point number in said first format prior to said adding step.

Claim 12

In a microprocessor, a method of converting a biased floating point number of a first kind having a fixed length exponent of a first length, to biased floating point number of a second kind having a fixed length exponent of a second length, said method comprising the steps of: coupling a microcode instruction to a decoder in response to a first clock pulse; decoding said microcode instruction to provide a first signal in response t a first phase of a first clock pulse; coupling said first signal to a controller in response to a second phase of said first clock pulse, said controller producing a second signal in response to said first signal which selects a predetermined constant from a read-only memory, said predetermined constant being selected prior to the end of said second phase of said first clock pulse; latching said exponent of said first length and said predetermined constant in response to a first phase of a second clock pulse; adding said predetermined constant, representative of the difference between said first length and said second length, to said exponent of said first kind to obtain a result which is said exponent of said second length; storng said result in a register in response to a second phase of said second clock pulse.

Claim 13

In a microprocessor, a method of converting a biased floating point number of a first kind having a fixed length exponent of a first length, to biased floating point number of a second kind having a fixed length exponent of a second length, said method comprising the steps of: coupling a microcode instruction to a decoder in response to a first clock pulse; decoding said microcode instruction to provide a first signal in response t a first phase of a first clock pulse; coupling said first signal to a controller in response to a second phase of said first clock pulse, said controller producing a second signal in response to said first signal which selects a predetermined constant from a read-only memory, said predetermined constant being selected prior to the end of said second phase of said first clock pulse; latching said exponent of said first length and said predetermined constant in response to a first phase of a second clock pulse; adding said predetermined constant, representative of the difference between said first length and said second length, to said exponent of said first kind to obtain a result which is said exponent of said second length; storng said result in a register in response to a second phase of said second clock pulse.

Claim 14

The method of claim 9 wherein said first length is 8-bits long, said predetermined constant is the hexidecimal number FF80 and said second length is 17-bits long.

Claim 15

The method of claim 9 wherein said first length is 11-bits long, said predetermined constant is the hexidecimal number FC00 and said second lengths is 17-bits long.

Claim 16

The method of claim 9 wherein said first length is 15-bits long, said predetermined constant is the hexidecimal number C000, and said second length is 17-bits long.

Claim 17

The method of claim 9 wherein said first length is 17-bits long, said predetermined constant is the hexidecimal number 14000 and said second length is 15-bits long.