US4701746A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for converting code signals of one bit number into a code signal of a smaller bit number
Assignee: Canon Inc
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Filing: 1985-09-05
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Granted: 1987-10-20
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Expires: 2005-09-05
Abstract
Abstract In a code converting device for converting first code data of scattered code form into second code data of consecutive data form, the first code data are divided at least into a first bit group and a second bit group, and the first bit group is supplied to a first memory to obtain first output data and second output data. The first output data and the second bit group are supplied to a second memory to obtain third output data. The second output data and the third output data are processed in a data processing unit to obtain the second code data.
Inventors
- 👤 Sigel Ueda
- 👤 Kozo Matsumoto
- 👤 Kiyoshi Kanaiwa
- 👤 Muneo Adachi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:05
CPC Classifications
H; H03; H03H; H03H7/00
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
190 words
A device for converting m-bit information signals into n-bit code signals, where n is smaller than m, the device comprising: input means for inputting m-bit information signals; first output means, which treats an m-bit information signal received from said input means as being in one of a plurality of groups comprising predetermined numbers of information signals, for choosing one of said groups using the input m-bit information signal and for generating a first order signal indicating the number, serially among all the groups of m-bit information signals, of the chosen group of information signals and a first identification signal indicating the locations of particular information signals in the chosen group of information signals; second output means for generating, in response to the first identification signal and a second identification signal derived from the input m-bit information signal, a second order signal indicating the number, serially among the particular information signals in the chosen group of information signals, of the input m-bit information signal; and obtaining means for obtaining an n-bit code signal, corresponding to the input m-bit information signal, by using the first order signal and the second order signal.
Claim 2
Independent Claim
190 words
A device for converting m-bit information signals into n-bit code signals, where n is smaller than m, the device comprising: input means for inputting m-bit information signals; first output means, which treats an m-bit information signal received from said input means as being in one of a plurality of groups comprising predetermined numbers of information signals, for choosing one of said groups using the input m-bit information signal and for generating a first order signal indicating the number, serially among all the groups of m-bit information signals, of the chosen group of information signals and a first identification signal indicating the locations of particular information signals in the chosen group of information signals; second output means for generating, in response to the first identification signal and a second identification signal derived from the input m-bit information signal, a second order signal indicating the number, serially among the particular information signals in the chosen group of information signals, of the input m-bit information signal; and obtaining means for obtaining an n-bit code signal, corresponding to the input m-bit information signal, by using the first order signal and the second order signal.
Claim 3
Dependent Claim
20 words
A device according to claim 1, wherein said first output means includes memory means for pre-storing the first order signal.
Claim 4
Dependent Claim
20 words
A device according to claim 1, wherein said second output means includes memory means for pre-storing the second order signal.
Claim 5
Dependent Claim
22 words
A device according to claim 1, wherein said obtaining means includes operation means for operating on the first and second order signals.
Claim 6
Dependent Claim
13 words
A device according to claim 2, wherein said memory means includes a RAM.
Claim 7
Dependent Claim
13 words
A device according to claim 3, wherein said memory means includes a ROM.
Claim 8
Independent Claim
164 words
A device for converting m-bit information signals into n-bit code signals, where n is smaller than m, the device comprising: first output means, which treats an input m-bit information signal as being in one of a plurality of groups comprising predetermined numbers of information signals, for choosing one of said groups using the input m-bit information signal and for generating a first order signal indicating the number, serially among all the groups of m-bit information signals, of the chosen group of information signals and a first identification signal indicating the locations of particular information signals in the chosen group of information signals; second output means for generating, in response to the first identification signal and a second identification signal derived from the input m-bit information signal, a second order signal indicating the arrangement of the input m-bit information signal in the chosen group; and forming means for forming a predetermined n-bit code signal by using the first order signal and the second order signal.
Claim 9
Independent Claim
164 words
A device for converting m-bit information signals into n-bit code signals, where n is smaller than m, the device comprising: first output means, which treats an input m-bit information signal as being in one of a plurality of groups comprising predetermined numbers of information signals, for choosing one of said groups using the input m-bit information signal and for generating a first order signal indicating the number, serially among all the groups of m-bit information signals, of the chosen group of information signals and a first identification signal indicating the locations of particular information signals in the chosen group of information signals; second output means for generating, in response to the first identification signal and a second identification signal derived from the input m-bit information signal, a second order signal indicating the arrangement of the input m-bit information signal in the chosen group; and forming means for forming a predetermined n-bit code signal by using the first order signal and the second order signal.
Claim 10
Dependent Claim
22 words
A device according to claim 7, wherein the first identification signal identifies a predetermined kind of m-bit information signal in each group.
Claim 11
Dependent Claim
28 words
A device according to claim 7, wherein said forming means forms at least two successive n-bit code signals in response to at least two non-successive m-bit information signals.
Claim 12
Independent Claim
175 words
A device for converting a plurality of m-bit information signals into n-bit code signals, where n is smaller than m, the device comprising: output means, which treats an input m-bit information signal as being in one of a plurality of groups comprising predetermined numbers of information signals, for choosing one of said groups using the input m-bit information signal and for generating a first identification signal indicating which m-bit information signals in the chosen group are of a first kind and which are of a second kind and a first order signal indicating the number, serially among all the groups of m-bit information signals, of the chosen group; means for generating a second order signal indicating the number, serially among all the information signals of the first kind in the chosen group, of the input m-bit information signal using the first identification signal and a second identification signal derived from the input m-bit information signal; and forming means for forming an n-bit code signal by using the first order signal and the second order signal.
Claim 13
Independent Claim
175 words
A device for converting a plurality of m-bit information signals into n-bit code signals, where n is smaller than m, the device comprising: output means, which treats an input m-bit information signal as being in one of a plurality of groups comprising predetermined numbers of information signals, for choosing one of said groups using the input m-bit information signal and for generating a first identification signal indicating which m-bit information signals in the chosen group are of a first kind and which are of a second kind and a first order signal indicating the number, serially among all the groups of m-bit information signals, of the chosen group; means for generating a second order signal indicating the number, serially among all the information signals of the first kind in the chosen group, of the input m-bit information signal using the first identification signal and a second identification signal derived from the input m-bit information signal; and forming means for forming an n-bit code signal by using the first order signal and the second order signal.
Claim 14
Dependent Claim
16 words
A device according to claim 10, wherein the information signals of the first kind represent characters.
Claim 15
Dependent Claim
21 words
A device according to claim 10, wherein said device converts a non-successive m-bit information signal into a successive n-bit code signal.
Claim 16
Independent Claim
257 words
A device for converting information signals each represented by a 16-bit character selected from information in a 16-bit table into 13-bit code signals, comprising: input means for serially inputting first and second 16-bit information signals representing two successive characters in the serial input, the first and second 16-bit information signals being non-succesive in the 16-bit table; first output means, which treats the 16-bit information signals received from said input means as being in a chosen one of a plurality of groups comprising predetermined numbers of information signals, for receiving the most significant 13 bits of each of the first and second 16-bit information signals input by said input means and generating a first order signal indicating the position among all the groups of 16-bit information signals, of the chosen group and a first identification signal indicating locations of information signals representing characters in the chosen group; second output means for generating a second order signal indicating the number, serially among the information signals representing characters in the chosen group, of each of the input 16-bit information signals using the first identification signal and the remaining 3 bits of each of the input 16-bit information signals; and summing means for summing the first order signal and the second order signal, wherein first and second 13-bit code signals, which are successive and correspond to the inputted first and second 16-bit information signals, are obtained by executing operations of said first and second output means and said summing means for each of the input first and second 16-bit information signals.
Claim 17
Independent Claim
257 words
A device for converting information signals each represented by a 16-bit character selected from information in a 16-bit table into 13-bit code signals, comprising: input means for serially inputting first and second 16-bit information signals representing two successive characters in the serial input, the first and second 16-bit information signals being non-succesive in the 16-bit table; first output means, which treats the 16-bit information signals received from said input means as being in a chosen one of a plurality of groups comprising predetermined numbers of information signals, for receiving the most significant 13 bits of each of the first and second 16-bit information signals input by said input means and generating a first order signal indicating the position among all the groups of 16-bit information signals, of the chosen group and a first identification signal indicating locations of information signals representing characters in the chosen group; second output means for generating a second order signal indicating the number, serially among the information signals representing characters in the chosen group, of each of the input 16-bit information signals using the first identification signal and the remaining 3 bits of each of the input 16-bit information signals; and summing means for summing the first order signal and the second order signal, wherein first and second 13-bit code signals, which are successive and correspond to the inputted first and second 16-bit information signals, are obtained by executing operations of said first and second output means and said summing means for each of the input first and second 16-bit information signals.
Claim 18
Dependent Claim
35 words
A device according to claim 13, wherein the first order signal indicates the number, serially among all of the 16-bit information signals, of the first 16-bit information signal representing a character in the chosen group.
References Cited (Backward Citations)
US4254463A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-19 | 1991-04-20 | 1991-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-19 | 1995-04-20 | 1995-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-19 | 1999-04-20 | 1999-10-20 | $7700.00 | Window Closed / Lapsed |