US4949162A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit with dummy pedestals
Assignee: Hitachi Ltd
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Filing: 1988-06-03
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Granted: 1990-08-14
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Expires: 2008-06-03
Abstract
Abstract A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).
Inventors
- 👤 Yoichi Tamaki
- 👤 Kiyoji Ikeda
- 👤 Toru Nakamura
- 👤 Akihisa Uchida
- 👤 Toru Koizumi
- 👤 Hiromichi Enami
- 👤 Satoru Isomura
- 👤 Shinji Nakajima
- 👤 Katsumi Ogiue
- 👤 Kaoru Ohgaya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 03:09
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/435; H10W20/495
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
229 words
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate having a main surface; (b) first generally parallel wiring channel regions extending in one direction over said main surface, said first wiring channel regions being arranged at a predetermined interval; (c) second generally parallel wiring channel regions extending in a vertical direction to said one direction over said main surface, said second wiring channel regions being arranged so that said first and second wiring channel regions form a wiring channel grid; (d) lower layer wirings formed along said wiring channel grid on said main surface, said lower layer wirings being comprised of a first conductive layer; (e) dummy pedestals comprised of the same conductive layer as that of said lower wirings, said dummy pedestals being formed on said main surface; (f) an inter-layer insulator film formed over said main surface so as to cover said lower layer wirings and said dummy pedestals; and (g) upper layer wirings formed along said first generally parallel wiring channel regions over said inter-layer insulator film, said upper layer wirings being comprised of a second conductive layer, wherein said dummy pedestals are provided respectively in intersecting areas of said first and second wiring channel regions in which none of said lower layer wirings is placed, and wherein said dummy pedestals are provided at least under areas in which said upper layer wirings are extended.
Claim 2
Dependent Claim
229 words
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate having a main surface; (b) first generally parallel wiring channel regions extending in one direction over said main surface, said first wiring channel regions being arranged at a predetermined interval; (c) second generally parallel wiring channel regions extending in a vertical direction to said one direction over said main surface, said second wiring channel regions being arranged so that said first and second wiring channel regions form a wiring channel grid; (d) lower layer wirings formed along said wiring channel grid on said main surface, said lower layer wirings being comprised of a first conductive layer; (e) dummy pedestals comprised of the same conductive layer as that of said lower wirings, said dummy pedestals being formed on said main surface; (f) an inter-layer insulator film formed over said main surface so as to cover said lower layer wirings and said dummy pedestals; and (g) upper layer wirings formed along said first generally parallel wiring channel regions over said inter-layer insulator film, said upper layer wirings being comprised of a second conductive layer, wherein said dummy pedestals are provided respectively in intersecting areas of said first and second wiring channel regions in which none of said lower layer wirings is placed, and wherein said dummy pedestals are provided at least under areas in which said upper layer wirings are extended.
Claim 3
Dependent Claim
28 words
A semiconductor integrated circuit device according to claim 1, wherein said second wiring channel regions are arranged at the same predetermined interval as said first wiring channel regions.
Claim 4
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 1, wherein each of said dummy pedestals has a plane configuration of a square.
Claim 5
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 1, wherein said first and second conductive layers are comprised of a material whose principal component is aluminum.
Claim 6
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 3, wherein adjacent dummy pedestals are arranged at a fixed interval along said one direction and said vertical direction.
Claim 7
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 5, wherein said inter-layer insulator film is formed so as to bury gaps between said adjacent dummy pedestals.
Claim 8
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 6, wherein said inter-layer insulator film is comprised of a silicon dioxide film.
Claim 9
Dependent Claim
30 words
A semiconductor integrated circuit device according to claim 1, wherein said lower layer wirings, said dummy pedestals and upper layer wirings are arranged by a computer-aided automatic wiring layout system.
Claim 10
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 1, wherein said dummy pedestals are electrically isolated from each other and from said lower layer wirings.
Claim 11
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 9, wherein each of said dummy pedestals is in a floating state electrically.
Claim 12
Dependent Claim
233 words
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate having a main surface; (b) first generally parallel imaginary lines extending in one direction over said main surface, said first lines being imaginarily formed by a computer-aided design system and being arranged at a predetermined interval; (c) second generally parallel imaginary lines extending in a vertical direction to said one direction over said main surface, said second lines being imaginarily formed by said system and being arranged so that said first and second lines form an imaginary grid; (d) lower layer wirings formed along said imaginary grid on said main surface, said lower layer wirings being comprised of a first conductive layer; (e) dummy pedestals comprised of the same conductive layer as that of said lower layer wirings, said dummy pedestals being formed on said main surface; (f) an inter-layer insulator film formed over said main surface so as to cover said lower layer wirings and said dummy pedestals; and (g) upper layer wirings formed along said first generally parallel imaginary lines over said inter-layer insulator film, said upper layer wirings being comprised of a second conductive layer, wherein said dummy pedestals are provided respectively in intersecting portions of said first and second lines in which none of said lower layer wirings is placed, and wherein said dummy pedestals are provided at least under areas in which said upper layer wirings are extended.
Claim 13
Dependent Claim
233 words
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate having a main surface; (b) first generally parallel imaginary lines extending in one direction over said main surface, said first lines being imaginarily formed by a computer-aided design system and being arranged at a predetermined interval; (c) second generally parallel imaginary lines extending in a vertical direction to said one direction over said main surface, said second lines being imaginarily formed by said system and being arranged so that said first and second lines form an imaginary grid; (d) lower layer wirings formed along said imaginary grid on said main surface, said lower layer wirings being comprised of a first conductive layer; (e) dummy pedestals comprised of the same conductive layer as that of said lower layer wirings, said dummy pedestals being formed on said main surface; (f) an inter-layer insulator film formed over said main surface so as to cover said lower layer wirings and said dummy pedestals; and (g) upper layer wirings formed along said first generally parallel imaginary lines over said inter-layer insulator film, said upper layer wirings being comprised of a second conductive layer, wherein said dummy pedestals are provided respectively in intersecting portions of said first and second lines in which none of said lower layer wirings is placed, and wherein said dummy pedestals are provided at least under areas in which said upper layer wirings are extended.
Claim 14
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 11, wherein each of said dummy pedestals has a plane configuration of a square.
Claim 15
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 12, wherein said first and second conductive layers are comprised of a material whose principal component is aluminum.
Claim 16
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 12, wherein adjacent dummy pedestals are arranged at a fixed interval along said one direction and said vertical direction.
Claim 17
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 14, wherein said inter-layer insulator film is formed so as to bury gaps between said adjacent dummy pedestals.
Claim 18
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 15, wherein said inter-layer insulator film is comprised of a silicon dioxide film.
Claim 19
Dependent Claim
28 words
A semiconductor integrated circuit device according to claim 11, wherein said lower layer wirings, said dummy pedestals and upper layer wirings are arranged by a computer-aided design system.
Claim 20
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 11, wherein said dummy pedestals are electrically isolated from each other and from the lower layer wirings.
Claim 21
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 18, wherein each of said dummy pedestals is in a floating state electrically.
Claim 22
Dependent Claim
28 words
A semiconductor integrated circuit device according to claim 11, wherein said second parallel imaginary lines are arranged at the same predetermined interval as said first parallel imaginary lines.
Claim 23
Dependent Claim
134 words
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate having a main surface; (b) lower layer wirings comprised of a first conductive layer formed on said main surface; (c) a plurality of dummy pedestals comprised of the same layer as said first conductive layer formed between said lower layer wirings on said main surface, each of said dummy pedestals having a plane configuration which is substantially square, adjacent ones of said dummy pedestals being spaced at a predetermined interval; (d) an inter-layer insulator film formed over said main surface so as to cover said lower layer wirings and said dummy pedestals; and (e) upper layer wirings comprised of a second conductive layer formed on said inter-layer insulator film, said upper layer wirings being extended over areas in which said dummy pedestals are formed.
Claim 24
Dependent Claim
134 words
A semiconductor integrated circuit device comprising: (a) a semiconductor substrate having a main surface; (b) lower layer wirings comprised of a first conductive layer formed on said main surface; (c) a plurality of dummy pedestals comprised of the same layer as said first conductive layer formed between said lower layer wirings on said main surface, each of said dummy pedestals having a plane configuration which is substantially square, adjacent ones of said dummy pedestals being spaced at a predetermined interval; (d) an inter-layer insulator film formed over said main surface so as to cover said lower layer wirings and said dummy pedestals; and (e) upper layer wirings comprised of a second conductive layer formed on said inter-layer insulator film, said upper layer wirings being extended over areas in which said dummy pedestals are formed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |