Patent US4949033A successfully refreshed from Google Patents.
US4949033A
Expired / Lapsed
US
⏱️ 0.0 years remaining
LSI system including a plurality of LSI circuit chips mounted on a board
Assignee: Fujitsu Ltd
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Filing: 1989-05-19
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Granted: 1990-08-14
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Expires: 2009-05-19
Abstract
Abstract An LSI system includes; a multi-layer print board; and a plurality of LSI circuit chips mounted on the multi-layer printed circuit board, each including a plurality of pins, a reference voltage terminal, a pin scan out terminal and a plurality of pin scan out circuits corresponding to the pins on a one-to-one basis. The multi-layer printed circuit board includes a reference voltage feeding layer formed therein in a form of a mesh or a sheet, at least one further layer overlying the reference voltage feeding layer and a plurality of through holes extending through each such further layer. By electrically connecting each reference voltage terminal of the plurality of LSI circuit chips through a corresponding through hole to the reference voltage feeding layer, a substantially equal reference voltage can be fed to each LSI and the voltage drop thereof is reduced.
Inventors
- 👤 Takeshi Kono
- 👤 Tatsuro Yoshimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:24
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2801; G01R31/2818; G01R31/316
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
197 words
An LSI system comprising: a multi-layer printed circuit board; and a plurality of LSI circuit chips mounted on said multi-layer printed circuit board, each including a plurality of pins, a reference voltage terminal, a pin scan out terminal and a plurality of pin scan out circuits corresponding to said pins on a one-to-one basis, each of said plurality of pin scan out circuits comparing a pin voltage appearing at a corresponding pin with a reference voltage appearing at said reference voltage terminal and outputting a signal indicating the result of said comparing in response to a pin select signal, said signal output from each pin scan out circuit being transmitted to said pin scan out terminal in a selection state of the corresponding LSI circuit chip, said multi-layer printed circuit board including a reference voltage feeding layer formed therein in a form of a mesh or a sheet, at least one further layer overlying the reference voltage feeding layer and a plurality of through holes extending through each such further layer, and each reference voltage terminal of said plurality of LSI circuit chips being electrically connected via a corresponding through hole to said reference voltage feeding layer.
Claim 2
Dependent Claim
197 words
An LSI system comprising: a multi-layer printed circuit board; and a plurality of LSI circuit chips mounted on said multi-layer printed circuit board, each including a plurality of pins, a reference voltage terminal, a pin scan out terminal and a plurality of pin scan out circuits corresponding to said pins on a one-to-one basis, each of said plurality of pin scan out circuits comparing a pin voltage appearing at a corresponding pin with a reference voltage appearing at said reference voltage terminal and outputting a signal indicating the result of said comparing in response to a pin select signal, said signal output from each pin scan out circuit being transmitted to said pin scan out terminal in a selection state of the corresponding LSI circuit chip, said multi-layer printed circuit board including a reference voltage feeding layer formed therein in a form of a mesh or a sheet, at least one further layer overlying the reference voltage feeding layer and a plurality of through holes extending through each such further layer, and each reference voltage terminal of said plurality of LSI circuit chips being electrically connected via a corresponding through hole to said reference voltage feeding layer.
Claim 3
Dependent Claim
71 words
An LSI system as set forth in claim 1, wherein each of said plurality of pin scan out circuits includes a comparator responding to said pin voltage and said reference voltage, each comparator of said plurality of pin scan out circuits being constituted by a specific portion of emitter coupled logic gate cells arrayed on a semiconductor chip, said specific portion being selected in the vicinity of said plurality of pins.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |