Digital carrier demodulator employing components working beyond normal limits

Claim 2

A digital carrier demodulator comprising: (a) analog to digital conversion means for receiving an intermediate frequency analog signal and for outputting a digital representation thereof; (b) sampling switch means for sampling said digital representation of said imtermediate frequency analog signal from said analog to digital conversion means and for outputting a pair of digital sample streams; (c) first multiplier means for multiplying one of said pair of digital sample streams with an in-phase carrier signal; (d) second multiplier means for multiplying the other of said pair of digital sample streams with a quadrature carrier signal; (e) first half-band digital low-pass filter means for filtering an output from said first multiplier means; (f) second half-band digital low-pass filter means for filtering an output from said second multiplier means; (g) first decimator means for decimating the number of samples from an output from said first half-band digital low-pass filter means; and, (h) second decimator means for decimating the number of samples from an output from said second half-band digital low-pass filter means, said first and second decimator means each having an output, said output of said first decimator means and said output of said second decimator means in combination comprising an output of the digital carrier demodulator; and wherein additionally, (i) said first and second half-band digital low-pass filter means each comprises, (i1) demultiplexer means for receiving a digital sample stream at an input thereof and for outputting a first output stream comprising odd samples from said digital sample stream and a second output stream comprising even samples from said digital sample stream, (i2) finite-impulse-response filter means having an input thereto and N taps to output data therefrom and being of order [(N+1)/2] for receiving and filtering said second output stream, (i3) delay means having an input and an output for receiving and delaying said first output stream for a time (in sampling periods) of [(N+1)/2]+r, where a pipeline delay through said finite-impulse-response filter means, and (i4) summing means for adding an output from said output of said delay means and an output from a center one of said taps of said filter means to produce a filtered output of said half-band digital low-pass filter means.

Claim 3

The digital carrier demodulator of claim 1 wherein: said finite-impulse-response filter means of order [(N+1)/2] is of an order less than the sampling frequency set by said sampling switch means for said pair of digital sample streams.

Claim 4

The digital carrier demodulator of claim 2 wherein: said finite-impulse-response filter means is of an order which is approximately half the sampling frequency set by said sampling switch means for said pair of digital sample streams.

Claim 5

In a digital carrier demodulator having, analog to digital conversion means for receiving an intermediate frequency analog signal and for outputting a digital representation thereof, sampling switch means for sampling the digital representation of the intermediate frequency analog signal from the analog to digital conversion means and for outputting a pair of digital sample streams, first multiplier means for multiplying one of the pair of digital sample streams with an in-phase carrier signal, and second multiplier means for multiplying the other of the pair of digital sample streams with a quadrature carrier signal the improvement comprising: (a) first half-band digital low-pass filter means for filtering an output from the first multiplier means; (b) second half-band digital low-pass filter means for filtering an output from the second multiplier means; (c) first decimator means for decimating the number of samples from an output from said first half-band digital low-pass filter means; and, (d) second decimator means for decimating the number of samples from an output from said second half-band digital low-pass filter means, said first and second decimator means each having an output, said output of said first decimator means and said output of said second decimator means in combination comprising an output of the digital carrier demodulator; and wherein additionally, (i) said first and second half-band digital low-pass filter means each comprises, (i1) demultiplexer means for receiving a digital sample stream at an input thereof and for outputting a first output stream comprising odd samples from said digital sample stream and a second output stream comprising even samples from said digital sample stream, (i2) finite-impulse-response filter means having an input thereto and N taps to output data therefrom and being of order [(N+1)/2] for receiving and filtering said second output stream, (i3) delay means having an input and an output for receiving and delaying said first output stream for a time (in sampling periods) of [(N+1)/2]+r, where r is a pipeline delay through said finite-impulse-response filter means, and (i4) summing means for adding an output from said output of said delay means and an output from a center one of said taps of said filter means to produce a filtered output of said half-band digital low-pass filter means.

Claim 6

In a digital carrier demodulator having, analog to digital conversion means for receiving an intermediate frequency analog signal and for outputting a digital representation thereof, sampling switch means for sampling the digital representation of the intermediate frequency analog signal from the analog to digital conversion means and for outputting a pair of digital sample streams, first multiplier means for multiplying one of the pair of digital sample streams with an in-phase carrier signal, and second multiplier means for multiplying the other of the pair of digital sample streams with a quadrature carrier signal the improvement comprising: (a) first half-band digital low-pass filter means for filtering an output from the first multiplier means; (b) second half-band digital low-pass filter means for filtering an output from the second multiplier means; (c) first decimator means for decimating the number of samples from an output from said first half-band digital low-pass filter means; and, (d) second decimator means for decimating the number of samples from an output from said second half-band digital low-pass filter means, said first and second decimator means each having an output, said output of said first decimator means and said output of said second decimator means in combination comprising an output of the digital carrier demodulator; and wherein additionally, (i) said first and second half-band digital low-pass filter means each comprises, (i1) demultiplexer means for receiving a digital sample stream at an input thereof and for outputting a first output stream comprising odd samples from said digital sample stream and a second output stream comprising even samples from said digital sample stream, (i2) finite-impulse-response filter means having an input thereto and N taps to output data therefrom and being of order [(N+1)/2] for receiving and filtering said second output stream, (i3) delay means having an input and an output for receiving and delaying said first output stream for a time (in sampling periods) of [(N+1)/2]+r, where r is a pipeline delay through said finite-impulse-response filter means, and (i4) summing means for adding an output from said output of said delay means and an output from a center one of said taps of said filter means to produce a filtered output of said half-band digital low-pass filter means.

Claim 7

The improvement to a digital carrier demodulator of claim 4 wherein: said finite-impulse-response filter means of order [(N+1)/2] is of an order less than the sampling frequency set by the sampling switch means for the pair of digital sample streams.

Claim 8

The improvement to a digital carrier demodulator of claim 5 wherein: said finite-impulse-response filter means is of an order which is approximately half the sampling frequency set by the sampling switch means for the pair of digital sample streams.

Claim 9

In a digital device having an input thereto comprising a digital sample stream at a frequency F, the method of employing a component therein designed to work at a frequency less than F comprising the steps of: (a) dividing the digital sample stream into odd and even digital sample streams each at a frequency of F/2; (b) passing one of the digital sample streams through the component designed to work at a frequency less than F wherein said component responds only to the odd or even digital samples in said one of the digital sample streams; (c) delaying the other of the digital sample streams for the time it takes the one of the digital sample streams to pass through the component; and, (d) adding the one of the digital sample streams after passing through the component with the delayed other of the digital sample streams.

Claim 10

In a digital device having an input thereto comprising a digital sample stream at a frequency F, the method of employing a component therein designed to work at a frequency less than F comprising the steps of: (a) dividing the digital sample stream into odd and even digital sample streams each at a frequency of F/2; (b) passing one of the digital sample streams through the component designed to work at a frequency less than F wherein said component responds only to the odd or even digital samples in said one of the digital sample streams; (c) delaying the other of the digital sample streams for the time it takes the one of the digital sample streams to pass through the component; and, (d) adding the one of the digital sample streams after passing through the component with the delayed other of the digital sample streams.

Claim 11

The method of claim 7 wherein the component is a finite-impulse-response filter having an input thereto and N taps to output data therefrom and being of order [(N+1)/2] and said step of delaying the other of the digital sample streams for the time it takes the one of the digital sample streams to pass through the component comrises: passing the other of the digital sample streams through a shift register for a time (in sampling periods) of [(N+1)/2]+r, where r is a pipeline delay through the finite-impulse-response filter.

Claim 12

In a digital carrier demodulator having an input thereto comprising a digital sample stream at a frequency F, the method of employing filters therein designed to work at a frequency less than F comprising the steps of: (a) demultiplexing the digital sample stream into odd and even digital sample streams each at a frequency of F/2; (b) passing the even digital sample stream through a finite-impulse-response filter having an input thereto and N taps to output data therefrom and being of order [(N+1)/2] and capable of working only at a frequency less than F; (c) passing the other of the digital sample streams through a shift register for a time of (in sampling periods) [(N+1)/2]+r, where r is a pipeline delay through the finite-impulse-response filter; and, (d) adding outputs of the finite-impulse-response filter and the shift register.

Claim 13

In a digital carrier demodulator having an input thereto comprising a digital sample stream at a frequency F, the method of employing filters therein designed to work at a frequency less than F comprising the steps of: (a) demultiplexing the digital sample stream into odd and even digital sample streams each at a frequency of F/2; (b) passing the even digital sample stream through a finite-impulse-response filter having an input thereto and N taps to output data therefrom and being of order [(N+1)/2] and capable of working only at a frequency less than F; (c) passing the other of the digital sample streams through a shift register for a time of (in sampling periods) [(N+1)/2]+r, where r is a pipeline delay through the finite-impulse-response filter; and, (d) adding outputs of the finite-impulse-response filter and the shift register.

Claim 14

The method of claim 9 wherein said step of adding outputs of the finite-impulse-response filter and the shift register comprises: adding an output from a center tap of the finite-impulse-response filter to an output from the shift register.