US4947229A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1987-11-23
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Granted: 1990-08-07
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Expires: 2007-11-23
Abstract
Abstract A semiconductor integrated circuit (IC) comprises a functional block which includes a plurality or first and second power source wiring layers arranged parallel to one another and formed so as to extend in a predetermined direction. A plurality of element regions are located between adjacent pairs of the first and second power source wiring layers. A cell block on the (IC) includes a plurality of cell column areas each having third and fourth power source wiring layers which are arranged parallel to each other and formed so as to extend in the predetermined direction. An element region is located between the third and fourth power source wiring layers. A plurality of wiring regions are located between adjacent cell column areas. A wiring interconnection section is also included for connecting the first and second power source wiring layers to the function block and includes a fifth power source wiring layer of double-layered structure having upper and lower layers respectively connected to the first and second power source wiring layers. The wiring interconnection section includes first and second segments which are also formed to extend in the predetermined direction, so as to connect the lower and upper layers of the fifth power source wiring layer to the third and fourth power source wiring layers.
Inventors
- 👤 Yutaka Tanaka
- 👤 Toshiki Morimoto
- 👤 Seiji Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:55
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
171 words
A semiconductor integrated circuit comprising: a functional block including a plurality of first and second power source wiring layers arranged substantially parallel to one another and formed to extend in a predetermined direction, a plurality of element regions each located between adjacent pairs of said first and second power source wiring layers, and a third power source wiring layer structure having upper and lower layers respectively connected to said first and second power source wiring layers; a cell block including a plurality of cell column areas each having fourth and fifth power source wiring layers arranged parallel to each other and formed to extend in said predetermined directio, an element region located between said fourth and fifth power source wiring layers, and a plurality of wiring regions, each located between adjacent cell column areas; and first and second interconnection members formed to extend in said predetermined direction, to connect said lower and upper layers of said third power source wiring layer structure to said fourth and fifth power source wiring layers.
Claim 2
Dependent Claim
171 words
A semiconductor integrated circuit comprising: a functional block including a plurality of first and second power source wiring layers arranged substantially parallel to one another and formed to extend in a predetermined direction, a plurality of element regions each located between adjacent pairs of said first and second power source wiring layers, and a third power source wiring layer structure having upper and lower layers respectively connected to said first and second power source wiring layers; a cell block including a plurality of cell column areas each having fourth and fifth power source wiring layers arranged parallel to each other and formed to extend in said predetermined directio, an element region located between said fourth and fifth power source wiring layers, and a plurality of wiring regions, each located between adjacent cell column areas; and first and second interconnection members formed to extend in said predetermined direction, to connect said lower and upper layers of said third power source wiring layer structure to said fourth and fifth power source wiring layers.
Claim 3
Dependent Claim
79 words
A semicondcutor integrated circuit according to claim 1, wherein said first power source wiring layers are formed integrally with the lower layer of said third power source wiring layer, and each of said second power source wiring layers has a first segment formed in substantially the same plane as said first power source wiring layers and a second segment formed integrally with the upper layer of said third power source wiring layer and electrically connected to said first segment.
Claim 4
Dependent Claim
51 words
A semiconductor integrated circuit according to claim 1, wherein said lower layer of said third power source wiring layer structure has first and second lower layer segments which are respectively connected to both ends of said first power source wiring layers and extend in a direction perpendicular to said predetermined direction.
Claim 5
Dependent Claim
82 words
A semiconductor integrated circuit according to claim 1, wherein said lower layer of third power source wiring layer structure has a first lower layer segment which is respectively connected to one end of each of said first power source wiring layers and extends in a direction perpendicular to said predetermined direction, and a second lower layer segment which is respectively connected to one end of each of said second power source wiring layers and extends parallel to said first lower layer segment.
Claim 6
Dependent Claim
68 words
A semiconductor integrated circuit according to claim 1, further comprising sixth and seventh power source wriing layers extending in a direction perpendicular to said prdetermined direction, said sixth wiring layers being formed integrally with at least one of said first powre source wiring layers, and said seventh power source wiring layer bieng formed to be electrically connected to at least one of said second power source wiring layers.
Claim 7
Dependent Claim
52 words
A semiconductor integrated circuit according to claim 5, wherein said lower layer of said third power source wiring layer structure is formed integrally with said sixth powr source wiring layers, and said upper layer of said third power source wiring layer structure is electrically connected to said seventh power source wiring layers.
References Cited (Backward Citations)
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JPS621248A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-06 | 1994-02-05 | 1994-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-06 | 1998-02-05 | 1998-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-06 | 2002-02-05 | 2002-08-07 | $7700.00 | Window Closed / Lapsed |