Level and edge sensitive input circuit

Claim 2

An input circuit for receiving signals on an input line, and functioning to control the state of a memory element, said circuit comprising: bias means comprising a transconductance amplifier coupled as a voltage follower to apply a bias voltage to said input line; first comparator means coupled to set the state of said memory element when said input signals are a predetermined increment above said bias voltage; and second comparator means coupled to reset the state of said memory element when said input signals are a predetermined increment below said bias voltage.

Claim 3

An input circuit for receiving signals on an input line, and functioning to control the state of a memory element, said circuit comprising: bias means including a high resistance element coupled in series with a voltage reference and connected to apply a bias voltage to said input line whereby said input line is biased at said voltage reference in the absence of any input signals; first comparator means coupled to set the state of said memory element when said input signals are a predetermined increment above said bias voltage; and second comparator means coupled to reset the state of said memory element when said input signals are a predetermined increment below said bias voltage.

Claim 4

An input circuit for receiving signals on an input line, and functioning to control the state of a memory element, said circuit comprising: bias means including a high resistance element coupled in series with a voltage reference and connected to apply a bias voltage to said input line whereby said input line is biased at said voltage reference in the absence of any input signals; first comparator means coupled to set the state of said memory element when said input signals are a predetermined increment above said bias voltage; and second comparator means coupled to reset the state of said memory element when said input signals are a predetermined increment below said bias voltage.

Claim 5

An input circuit as recited in claim 2, wherein said memory element comprises a toggle flip-flop.

Claim 6

A level and edge sensitive input circuit for receiving an input signal on an input line, said circuit comprising: (a) a transconductance amplifier connected as a voltage follower having its output connected to its inverting input and to said input line and its noninverting input connected to a source of bias voltage whereby said input line is operated at said bias voltage in the absence of any input signal; (b) a toggle flip-flop with a toggle input, a reset input and an output; (c) a first comparator with first and second inputs and an output, with said first input coupled to said input line, said second input coupled to a first voltage reference higher than said bias voltage and said output coupled to said toggle input of said toggle flip-flop; and (d) a second comparator with first and second inputs and an output, with said first input coupled to said input line, said second input coupled to a second voltage reference lower than said bias voltage, and said output coupled to said reset input of said toggle flip-flop.

Claim 7

A level and edge sensitive input circuit for receiving an input signal on an input line, said circuit comprising: (a) a transconductance amplifier connected as a voltage follower having its output connected to its inverting input and to said input line and its noninverting input connected to a source of bias voltage whereby said input line is operated at said bias voltage in the absence of any input signal; (b) a toggle flip-flop with a toggle input, a reset input and an output; (c) a first comparator with first and second inputs and an output, with said first input coupled to said input line, said second input coupled to a first voltage reference higher than said bias voltage and said output coupled to said toggle input of said toggle flip-flop; and (d) a second comparator with first and second inputs and an output, with said first input coupled to said input line, said second input coupled to a second voltage reference lower than said bias voltage, and said output coupled to said reset input of said toggle flip-flop.

Claim 8

A level and edge sensitive input circuit for receiving an input signal on an input line, said circuit comprising: (a) a high resistance coupled in series with a voltage reference and connected to said input line whereby said input line is operated at a bias voltage equal to said reference voltage in the absence of any input signal; (b) a toggle flip-flop having a toggle input, a reset input and an output; (c) a first comparator with first and second inputs and an output with said first input coupled to said input line, said second input coupled to a voltage reference higher than said bias voltage and said output coupled to said toggle input of said toggle flip flop; and (d) a second comparator with first and second inputs and an output, with said first input coupled to said input line, said second input coupled to a second voltage reference lower than said bias voltage, and said output coupled to said reset input of said toggle flip-flop.

Claim 9

A level and edge sensitive input circuit for receiving an input signal on an input line, said circuit comprising: (a) a high resistance coupled in series with a voltage reference and connected to said input line whereby said input line is operated at a bias voltage equal to said reference voltage in the absence of any input signal; (b) a toggle flip-flop having a toggle input, a reset input and an output; (c) a first comparator with first and second inputs and an output with said first input coupled to said input line, said second input coupled to a voltage reference higher than said bias voltage and said output coupled to said toggle input of said toggle flip flop; and (d) a second comparator with first and second inputs and an output, with said first input coupled to said input line, said second input coupled to a second voltage reference lower than said bias voltage, and said output coupled to said reset input of said toggle flip-flop.

Claim 10

An input circuit as recited in claim 4, wherein said first voltage reference is higher than said bias voltage and comprises: first and second transistors each having emitter and base electrodes; means for operating said first and second transistors at different current densities; means responsive to the difference in base to emitter voltage of said first and second transistors and means to combine said difference in base to emitter voltages of said first and second transistors with said bias voltage to create said first voltage reference.

Claim 11

An input circuit as recited in claim 4, wherein said second voltage reference is lower than said bias voltage and comprises: first and second transistors each having an emitter and base electrodes; means for operating said first and second transistors at different current densities; means responsive to the difference in base to emitter voltages of said first and second transistors; and means to combine said difference in base to emitter voltages of said first and second transistors with said bias voltage to create said second voltage reference.

Claim 12

An input circuit as recited in claim 4, wherein said output of said second comparator is coupled to said reset input of said toggle flip-flop through an OR gate with first and second inputs and an output, with said OR gate first input coupled to said output of said second comparator, said OR gate second input coupled to a power-on reset signal, and said OR gate output coupled to said reset input of said toggle flip-flop.