US4943965A
Expired / Lapsed
US
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Digital signal decoding method and circuit therefor
Assignee: Mitsubishi Electric Corp
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Filing: 1988-07-11
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Granted: 1990-07-24
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Expires: 2008-07-11
Abstract
Abstract A digital signal decoding method and a circuit therefor which, when each data of first and second 1-bit of a set of 3-bit data received is a logical "1", decodes the data to 1-bit data of "1". When each of the data of the first and second 1-bit is "0", decodes the data to 1-bit data of "0". And when first and second 1-bit data is a combination of "1" and "0", directly decodes a third bit, thereby enabling a quick decoding result to be obtained when receiving the data.
Inventors
- 👤 Hirohisa Machida
- 👤 Takeo Nakabayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; H; H03; H03M; H03M5/00; H03M5/02; H03M5/04; H03M5/14; H03M5/145; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
145 words
A method for decoding an encoded 3-bit digital data signal to a 1-bit digital data signal, comprising the steps of: receiving the encoded 3-bit digital data signal from an external source; determining whether a first bit of the 3-bit digital data signal is a logical "1"; determining whether a second bit of the 3-bit digital data signal is a logical "1"; setting the 1-bit digital data signal to a "1" if said first bit and said second bit are both a logical "1"; setting the 1-bit digital data signal to a "0" if said first bit and said second bit are both a logical "0"; decoding a third bit of the 3-bit digital data signal directly if said first bit and said second bit are not both a logical "1" or a logical "0"; and transmitting the 1-bit digital data signal to an external destination.
Claim 2
Independent Claim
145 words
A method for decoding an encoded 3-bit digital data signal to a 1-bit digital data signal, comprising the steps of: receiving the encoded 3-bit digital data signal from an external source; determining whether a first bit of the 3-bit digital data signal is a logical "1"; determining whether a second bit of the 3-bit digital data signal is a logical "1"; setting the 1-bit digital data signal to a "1" if said first bit and said second bit are both a logical "1"; setting the 1-bit digital data signal to a "0" if said first bit and said second bit are both a logical "0"; decoding a third bit of the 3-bit digital data signal directly if said first bit and said second bit are not both a logical "1" or a logical "0"; and transmitting the 1-bit digital data signal to an external destination.
Claim 3
Dependent Claim
240 words
A digital data signal decoding circuit in which individual bits of a 3-bit digital data signal are input to first, second, and third signal lines wherein the 3-bit digital data signal is decoded into a 1-bit digital data signal and output on a fourth signal line, comprising: detection means for detecting a logical value of the individual bits of the 3-bit digital data signal input on the first and second signal lines and for outputting a first detection signal if the first and second signal lines are both a logical "1", for outputting a second detection signal if the first and second signal lines are both a logical "0", and for outputting a third detection signal if the first and second signal lines are a combination of a logical "1" and a logical "0"; first signal generating means for receiving said first detection signal from said detection means and generating a logical "1" in response to said first detection signal to be output on the fourth signal line; second signal generating means for receiving said second detection signal from said detection means and generating a logical "0" in response to said second detection signal to be output on the fourth signal line; and gate means connected to receive said third detection signal for receiving an input signal on the third signal line and providing said input signal on the fourth signal line in response to receiving said third detection signal.
Claim 4
Dependent Claim
240 words
A digital data signal decoding circuit in which individual bits of a 3-bit digital data signal are input to first, second, and third signal lines wherein the 3-bit digital data signal is decoded into a 1-bit digital data signal and output on a fourth signal line, comprising: detection means for detecting a logical value of the individual bits of the 3-bit digital data signal input on the first and second signal lines and for outputting a first detection signal if the first and second signal lines are both a logical "1", for outputting a second detection signal if the first and second signal lines are both a logical "0", and for outputting a third detection signal if the first and second signal lines are a combination of a logical "1" and a logical "0"; first signal generating means for receiving said first detection signal from said detection means and generating a logical "1" in response to said first detection signal to be output on the fourth signal line; second signal generating means for receiving said second detection signal from said detection means and generating a logical "0" in response to said second detection signal to be output on the fourth signal line; and gate means connected to receive said third detection signal for receiving an input signal on the third signal line and providing said input signal on the fourth signal line in response to receiving said third detection signal.
Claim 5
Dependent Claim
191 words
The digital data signal decoding circuit of claim 2 wherein said detection means further comprises: a NOR gate having a first input connected to said first signal line, a second input connected to said second signal line, and an output for providing said second detection signal to said second signal generating means; a first NAND gate having a first input connected to said first signal line, a second input connected to said second signal line, and an output for providing said first detection signal to said first signal generating means; a first inverter having an input connected to said output of said NOR gate and an output; a second NAND gate having a first input connected to said output of said first inverter, a second input connected to said output of said first NAND gate, and an output connected to said gate means for providing said third detection signal to said gate means; and a second inverter having an input connected to said output of said second NAND gate and an output connected to said gate means for providing an inverted version of said third detection signal to said gate means.
Claim 6
Dependent Claim
52 words
The digital data signal decoding circuit of claim 2 wherein said first signal generating means further comprises: a first p-type gate element having a drain connected to an active signal, a source connected to the fourth signal line, and a gate connected to said detection means for receiving said first detection signal.
Claim 7
Dependent Claim
50 words
The digital data signal decoding circuit of claim 2 wherein said second signal generating means further comprises: a first n-type gate element having a drain connected to the fourth signal line, a source connected to ground, and a gate connected to said detection means for receiving said second detection signal.
Claim 8
Dependent Claim
92 words
The digital data signal decoding circuit of claim 2 wherein said gate means further comprises: a second n-type gate element having a drain connected to the third signal line, a source connected to the fourth signal line, and a gate connected to said detection means for receiving said third detection signal; and a second p-type gate element having a drain connected to the third signal line, a source connected to the fourth signal line, and a gate connected to said detection means for receiving an inverted version of said third detection signal.
Claim 9
Dependent Claim
32 words
The digital data signal decoding circuit of claim 2 wherein said detecting means, said first signal generating means, said second signal generating means, and said gate means are situated on one chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-23 | 1994-01-22 | 1994-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-23 | 1998-01-22 | 1998-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-23 | 2002-01-22 | 2002-07-24 | $7700.00 | Window Closed / Lapsed |