Patent US4943786A successfully refreshed from Google Patents.
US4943786A
Expired / Lapsed
US
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Digital control of phase locked loops
Assignee: Telent Technologies Services Ltd
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Filing: 1988-09-01
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Granted: 1990-07-24
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Expires: 2008-09-01
Abstract
Abstract A control circuit, particularly for use in a phase-locked loop includes a read-only memory (ROM) having n address inputs divided into two groups, each group being addressed by first (A) and second (B) signals, and the memory device having words preprogrammed therein to provide an output having values (C) of a predetermined function of the first and second signals. In one embodiment the control circuit is employed in a phase-locked loop where one address group provides an analog version of the first signal to a voltage controlled oscillator, and application of the second signal to the second address group permits a step change in the output voltage to the VCO. In another embodiment, the first and second signals may comprise carrier signals and modulating signals in a phase-locked loop employed for frequency modulation.
Inventors
- 👤 Brian Cordwell
- 👤 Paul M. Hayes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:58
CPC Classifications
G; G06; G06J; G06J1/00; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0342; G06F7/00; G06F7/02; G06F7/026; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/093; H03L7/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
190 words
A phase locked loop circuit, the circuit including a phase comparator having first and second inputs and an output, a voltage controlled oscillator, having an input and output, and a control circuit having input means and output means, the first input of the phase comparator being coupled to a reference source, the second input of the phase comparator being coupled to the output of the voltage controlled oscillator, the output of the phase comparator being coupled to said input means of the control circuit, and the output means of the control circuit being coupled to the input of the voltage controlled oscillator; the control circuit comprising a signal translating device, the device having n binary signals inputs and a predetermined number of binary signal outputs; the signal inputs comprising first and second address groups, first and second signal means for applying first (A) and second (B) binary signals to the inputs of the respective first and second address groups; the signal translating device providing a signal translating function such that said binary signal output are provided which are a predetermined function (C) of the first and second signals (A, B).
Claim 2
Dependent Claim
190 words
A phase locked loop circuit, the circuit including a phase comparator having first and second inputs and an output, a voltage controlled oscillator, having an input and output, and a control circuit having input means and output means, the first input of the phase comparator being coupled to a reference source, the second input of the phase comparator being coupled to the output of the voltage controlled oscillator, the output of the phase comparator being coupled to said input means of the control circuit, and the output means of the control circuit being coupled to the input of the voltage controlled oscillator; the control circuit comprising a signal translating device, the device having n binary signals inputs and a predetermined number of binary signal outputs; the signal inputs comprising first and second address groups, first and second signal means for applying first (A) and second (B) binary signals to the inputs of the respective first and second address groups; the signal translating device providing a signal translating function such that said binary signal output are provided which are a predetermined function (C) of the first and second signals (A, B).
Claim 3
Dependent Claim
49 words
A circuit according to claim 1, wherein the signal translating device comprises a memory device having words preprogrammed therein which are addressed by said first and second address groups to provide an output having values which represent values of a predetermined function (C) of the first and second signals.
Claim 4
Dependent Claim
47 words
A circuit according to claim 2 wherein said words are preprogrammed according to the difference between the values of the first and secondary signals (A-B), such that the values are scaled against one another and said function is such that C=A(kB).sup.±1, where k is a constant factor.
Claim 5
Dependent Claim
59 words
A circuit as claimed in claim 2 wherein sais memory device comprises a first storage area comprising n addressable words and a second storage area comprising n addressable words, wherein the signals applied to said first and second signal groups determine whether words from said first or second storage areas are provided as an output of the memory device.
Claim 6
Dependent Claim
102 words
A circuit according to claim 2 wherein said memory device has n address inputs to effect addressing of 2 n addressable words; said first address group comprises n/2 of said n address inputs; and said second address group comprises a different n/2 of said n address inputs and each of said 2 n addressable word stores a respective predetermined value derived from a comparison between a value output by said first address group and a value output by said second address group which values in combination address one of said 2 n addressable words to cause output of said respective predetermined value.
Claim 7
Dependent Claim
59 words
A circuit according to claim 1 wherein said first and second signal means comprise respective first and second analog to digital converters for receiving analog versions of the first and second signals and the control circuit including a digital to analog converter to which the output of the signal translating device is supplied to provide an analog output signal.
Claim 8
Dependent Claim
68 words
A circuit according to claim 6 wherein said output of the digital to analog converter is connected for control of the voltage controlled oscillator, the output of the phase comparator providing said first binary signal (A) and being connected to said first analog to digital converter, and said second signal (B) providing a modulating signal for the phase locked loop applied to said second analog to digital converter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-23 | 1994-01-22 | 1994-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-23 | 1998-01-22 | 1998-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-23 | 2002-01-22 | 2002-07-24 | $7700.00 | Window Closed / Lapsed |