Differentiating logical circuit for asynchronous systems

Claim 2

A digital logic circuit comprising: means for receiving at least one input signal X; means connected to said receiving means and responsive to a change of logic level of said at least one input signal X to produce a change of logic level in an output signal Y from a rest logic level to another logic level; means for receiving at least one feedback signal F from a circuit utilizing said output signal Y; and means connected to said feedback signal receiving means and responsive to a change of logic level in said feedback signal F to return said output signal Y back to said rest logic level.

Claim 3

A digital logic circuit as in claim 1, wherein said means for producing a change in logic level of said output signal Y from said rest logic level operates independently of the logic level of said feedback signal F.

Claim 4

A digital logic circuit as in claim 2, which comprises a first gate for receiving said input signal X, and a first flip-flop having one input receiving said input signal X and another input responsive to said at least one feedback signal F, said first gate also receiving as an input an output signal P of said first flip-flop.

Claim 5

A digital logic circuit as in claim 3, further comprising a second flip-flop having one input receiving said output signal Y and another input receiving said at least one feedback signal F, a second gate having one input receiving an output S of said second flip-flop and another input receiving said at least one feedback signal F, the output of said second gate being applied to said another input of said first flip-flop.

Claim 6

A digital logic circuit as in claim 1, further comprising means for producing a feedback signal E for another circuit from said outpu signal Y.

Claim 7

A digital logic circuit as in claim 5, wherein said means for producing said feedback signal E is an inverter.

Claim 8

A digital logic circuit as in claim 4, which has the logical equation: Y=X∩P∩(F∩S∩Y) where ∩ represents a logical AND function, and ∩ represents the inverse of a logical AND function.

Claim 9

A digital logic circuit as in claim 1, wherein said means for producing a change in logic level of said output signal Y from said rest logic level operates in dependence on the current logic level of said feedback signal F such that said feedback signal F must have a predetermined logic level during said change of logic level of input signal X to permit a change in logic level of output signal Y from said rest logic level.

Claim 10

A digital logic circuit as in claim 8, which comprises a first gate responsive to said input signal X, and a first flip-flop having one input responsive to said input signal X and another input responsive to said at least one feedback signal F, said first gate having another input for receiving an output signal P of said first flip-flop.

Claim 11

A digital logic circuit as in claim 9, further comprising an inverter for inverting said at least one feedback signal F and for supplying an inverted feedback signal F to said another input of said first flip-flop.

Claim 12

A digital logic circuit as in claim 10, having the logical equation: Y=X∩(P∩F) where ∩ represents a logical AND function.

Claim 13

A digital logic circuit as in claim 11, wherein said first gate has a third input thereto which receives the output signal of said inverter.

Claim 14

A digital logic circuit as in claim 1, wherein said means for receiving said at least one input signal X is an AND gate which receives a plurality of input signals and said means for producing a change in logic level of said output signal Y from said rest logic level produces said change in response to a change of output logic level of said AND gate.

Claim 15

A digital logic circuit as in claim 10, further comprising an AND gate having respective inputs for receiving a plurality of input signals X 1 . . . X n , said first gate receiving the output signal of said AND gate, said first flip-flop at said one input thereof also receiving the output of said AND gate, said digital logical circuit having the logical equation: (X 1 ∩X 2 ∩. . . X)∩(P∩F), where ∩ represents a logical AND function.

Claim 16

A digital logic circuit as in claim 2, wherein said means for receiving at least one input signal receives a plurality of input signals X 1 . . . X n and said means responsive to a change of logic level produces said change of logic level of said output signal Y by performing a logical AND function on said input signals.

Claim 17

A digital logic circuit as in claim 8, wherein said means for receiving at least one input signal receives a plurality of input signals X 1 . . . X n and said means responsive to a change of logic level produces said change of logic level of said output signal Y by performing a logical AND function on said input signals.

Claim 18

A digital logic circuit as in claim 2, wherein said means for receiving at least one input signal receives a plurality of input signals X 1 . . . X n , and said means responsive to a change of logic level produces said change of logic level of said output signal Y by performing a logical OR function on said input signals.

Claim 19

A digital logic circuit as in claim 8, wherein said means for receiving at least one input signal receives a plurality of input signals X 1 . . . X n , and said means responsive to a change of logic level produces said change of logic level of said output signal Y by performing a logical OR function on said input signals.

Claim 20

A digital logic circuit as in claim 15, further comprising means for inverting said output signal Y.

Claim 21

A digital logic circuit as in claim 16, further comprising means for inverting said output signal Y.

Claim 22

A digital logic circuit as in claim 17, further comprising means for inverting said output signal Y.

Claim 23

A digital logic circuit as in claim 18, further comprising means for inverting said output signal Y.

Claim 24

A digital logic circuit as in claim 2, which comprises a first gate responsive to said input signal X, and a first flip-flop having one input responsive to said input signal X and another input responsive to said at least one feedback signal F, said first gate having another input for receiving an output signal P of said first flip-flop.

Claim 25

A digital logic circuit as in claim 23, further comprising an inverter for inverting said at least one feedback signal F and for supplying an inverted feedback signal F to said another input of said first flip-flop.

Claim 26

A digital logic circuit as in claim 15, which comprises a first AND gate for receiving a plurality of applied input signals X 1 . . . X n , a flip-flop having one input receiving the output of said first AND gate an another input responsive to said at least one feedback signal, a second AND gate having a first input for receiving an output signal of said first AND gate, and a second input for receiving an output of said flip-flop, said output signal Y being taken from an output of said second AND gate.

Claim 27

A digital logic circuit as in claim 16, which comprises a first AND gate for receiving a plurality of applied input signals X 1 . . . X n , a flip-flop having one input receiving the output of said first AND gate and another input responsive to said at least one feedback signal, a second AND gate having a first input for receiving an output signal of said first AND gate, a second input for receiving an output of said flip-flop and a third input responsive to said at least one feedback signal, said output signal Y being taken from an output of said second AND gate.

Claim 28

A digital logic circuit as in claim 15, which comprises an AND gate having inputs respectively receiving said input signals X 1 . . . X n , and a flip-flop formed by cross-coupled NAND gates, one of said NAND gates having respective inputs receiving said input signals X 1 . . . X n and another input receiving an output of another NAND gate, said AND gate having an input for receiving an output of said one NAND gate, said another NAND gate having one input connected to be responsive to said at least one feedback signal and another input receiving the output from said one NAND gate.

Claim 29

A digital logic circuit as in claim 16, which comprises an AND gate having inputs respectively receiving said input signals X 1 . . . X n , and a flip-flop formed by cross-coupled NAND gates, one of said NAND gates having respective inputs receiving said input signals X 1 . . . X n and another input receiving the output of another NAND gate, said AND gate having an input for receiving an output of said one NAND gate, said another NAND gate having one input connected to be responsive to said at least one feedback signal and another input receiving the output from said one NAND gate, said AND gate having another input responsive to said at least one feedback signal.

Claim 30

A digital logic circuit as in claim 17, which comprises an OR gate having inputs for receiving respective input signals X 1 . . . X n , a flip-flop having one input receiving the output of said OR gate and another input responsive to said at least one feedback signal, and an AND gate having one input for receiving an output of said OR gate, and another input for receiving an output of said flip-flop.

Claim 31

A digital logic circuit as in claim 18, which comprises an OR gate having inputs for receiving respective input signals X 1 . . . X n , a flip-flop having one input receiving the output of said OR gate and another input responsive to said at least one feedback signal, and an AND gate having one input for receiving an output of said OR gate, another input for receiving an output of said flip-flop, and another input responsive to said at least one feedback signal.

Claim 32

A digital logic circuit as in claim 29, which has the logical equation Y=(X 1 ∪X 2 ∩. . . X n )∩(P∩F), where ∪ represents a logical OR function and ∩ represents a logical AND function.

Claim 33

A digital logic circuit as in claim 30, which has the logical equation Y=(X 1 ∪X 2 ∪. . . X n )∩(P∩F), where ∪ represents a logical OR function and ∩ represents a logical AND function.

Claim 34

A digital logic circuit as in claim 18, comprising a plurality of NAND gates each having a first input respectively receiving one of said applied input signals X 1 . . . X n , a plurality of AND gates, each having one input for receiving a respective input signal X 1 . . . X n and another input for receiving a respective output from said plurality of NAND gates, another NAND gate cross-coupled to said plurality of NAND gates to form a flip-flop, an output of said another NAND gate being supplied commonly to second inputs of said plurality of NAND gates, said another NAND gate having one input responsive to said at least one feedback signal and a plurality of other inputs respectively receiving outputs of said plurality of NAND gates, and an OR gate having a plurality of inputs respectively receiving outputs of said AND gates, said output signal Y being taken at an output of said OR gate, said AND gates also having respective inputs responsive to said at least one feedback signal.

Claim 35

A digital logic circuit as in claim 33, having the logical equation: Y=(X.sub.1 ∩P.sub.1 ∩F)∪(X.sub.2 ∩P.sub.2 ∩F)∪. . . (X.sub.n ∩P.sub.n ∩F).

Claim 36

A digital logic circuit as in claim 18, comprising a plurality of NAND gates each having a first input respectively receiving one of said applied input signals X 1 . . . X n , a plurality of AND gates, each having one input for receiving a respective input signal X 1 . . . X n and another input for receiving a respective output from said pluarlity of NAND gates, another NAND gate cross-coupled to said plurality of NAND gates to form a flip-flop, an output of said another NAND gate being supplied commonly to second inputs of said plurality of NAND gates, said another NAND gate having one input responsive to said at least one feedback signal and a plurality of other inputs respectively receiving outputs of said plurality of NAND gates, and an OR gate having a plurality of inputs respectively receiving the outputs of said AND gates, said output signal Y being taken at an output of said OR gate.

Claim 37

A digital logic circuit as in claim 35, having the logical equation: Y=(X.sub.1 ∩P.sub.1 ∩F)∪(X.sub.2 ∩P.sub.2 ∩F)∪. . . (X.sub.n ∩P.sub.n ∩F).

Claim 38

A digital logic circuit as in claim 2, wherein said means for receiving at least one input signal X receives a plurality of input signals X 1 . . . X n and said means for producing a change in logic level of said output signal Y from said rest logic level produces said change in response to a predetermined logical combination of the logic levels of said input signals.

Claim 39

A digital logic circuit as in claim 37, wherein said predetermined logical combination is an AND function.

Claim 40

A digital logic circuit as in claim 37, wherein said predetermined logical combination is an OR function.

Claim 41

A digital logic circuit as in claim 37, wherein said predetermined logical combination is an XOR function.

Claim 42

A digital logic circuit as in claim 37, wherein said predetermined logical combination is a NAND function.

Claim 43

A digital logic circuit as in claim 37, wherein said predetermined logical combination is a NOR function.

Claim 44

A digital logic circuit as in claim 8, wherein said means for receiving at least one input signal X receives a plurality of input signals X 1 . . . X n and said means for producing a change in logic level of said output signal Y from said rest logic level produces said change in response to a predetermined logical combination of the logic levels of said input signals.

Claim 45

A digital logic circuit as in claim 43, wherein said predetermined logical combination is an AND function.

Claim 46

A digital logic circuit as in claim 43, wherein said predetermined logical combination is an OR function.

Claim 47

A digital logic circuit as in claim 43, wherein said predetermined logical combination is an XOR function.

Claim 48

A digital logic circuit as in claim 43, wherein said predetermined logical combination is a NAND function.

Claim 49

A digital logic circuit as in claim 43, wherein said predetermined logical combination is a NOR function.