ECL/CML emitter follower current switch circuit

Claim 2

An improved emitter coupled logic or current mode logic (ECL/CML) circuit having a first active switching node providing true output signals of high and low potential, first emitter follower transistor means coupled to the first active switching node for sourcing said true output signals to a first output, a second active switching node providing complementary output signals of low and high potential, second emitter follower transistor means coupled to the second active switching node for sourcing said complementary output signals to a second output, and output current sink means operatively coupled for sinking current from the first and second outputs and first and second emitter follower transistor means, the improvement comprising: an emitter follower current switch circuit comprising a first current switch transistor element operatively coupled between the first emitter follower transistor means and the output current sink means and a second current switch transistor element operatively coupled between the second emitter follower transistor means and said output current sink means; a first control circuit arranged and coupled for controlling the conducting state of the first current switch transistor element so that it is on and off for true output signals of low and high potential respectively, said first emitter follower transistor means and output thereby being substantially disconnected from the output current sink means when the first output is at high potential; a second control circuit arranged and coupled for controlling the conducting state of the second current switch transistor element so that it is on and off (non conducting) for true output signals of high and low potential respectively, said second emitter follower transistor means and second output thereby being substantially disconnected from the output current sink means when the second output is at high potential; said first control circuit comprising a first potential difference circuit element operatively coupled between the emitter node of the second emitter follower transistor means and the base node of the first current switch transistor element and said second control circuit comprising a second potential difference circuit element operatively coupled between the emitter node of the first emitter follower transistor means and the base node of the second current switch transistor element.

Claim 3

The ECL/CML circuit of claim 1 wherein the first emitter follower transistor means comprises a first emitter follower transistor element for sourcing true output signals of high and low potential to the first output and a second control circuit emitter follower transistor element coupled in the second control circuit for the controlling the conducting state of the second current switch transistor element, and wherein the second emitter follower transistor means comprises a second emitter follower transistor element operatively coupled for sourcing the complementary output signals of low and high potential to the second output and a first control circuit emitter follower transistor element operatively coupled in the first control circuit for controlling the conducting state of the first current switch transistor element.

Claim 4

The ECL/CML circuit of claim 2 wherein the first control circuit comprises a first potential difference circuit element coupling the emitter node of the first control circuit emitter follower transistor element to the base node of the first current switch transistor element and wherein the second control Circuit comprises a second potential difference circuit element operatively coupling the emitter node of the second control circuit emitter follower transistor element to the base node of the second current switch transistor element.

Claim 5

The ECL/CML circuit of claim 2 further comprising control circuit current sink means operatively coupled for sinking current from the first and second control circuit current sink means also being operatively coupled to base nodes of the first and second current switch transistor elements for discharging the respective bases of the first and second current switch transistor elements.

Claim 6

The ECL/CML circuit of claim 4 wherein the current sinking capacity of the output current sink means is substantially greater than the current sinking capacity of the control circuit sink means.

Claim 7

An improved emitter coupled logic or current mode logic (ECL/CML) circuit having active switching first and second output nodes respectively providing true and complementary output signals of high and low potential, output buffer first and second emitter follower transistor means operatively coupled respectively to the first and second output nodes for sourcing said output signals to respective true and complementary outputs, and output current sink means operatively coupled for sinking current respectively from the true output and first emitter follower transistor means and from the complementary output and second emitter follower transistor means, the improvement comprising: first current switch transistor element operatively coupled between the first emitter follower transistor means said output current sink means; first cross-control circuit coupled between the emitter node of the second emitter follower transistor means and the base node of the first current switch transistor element for controlling the conducting state of the first current switch transistor element so that it is on (conducting) and off (non-conducting) for complementary output signals of high and low potential respectively; second current switch transistor element operatively coupled between the second emitter follower transistor means and said output current sink means; and second cross-control circuit coupled between the emitter node of the first emitter follower transistor means and the base node of the second current switch transistor element for controlling the conducting state of the second current switch transistor element so that it is on (conducting) and off (non-conducting) for true output signals of high and low potential respectively; said first emitter follower transistor means comprising a true output emitter follower transistor element coupled to the true output and a second cross-control circuit emitter follower transistor element coupled to control the conducting state of the second current switch transistor element, and said second emitter follower transistor means comprising a complementary output emitter follower transistor element coupled to the complementary output and a first cross-control circuit emitter follower transistor element coupled to control the conducting state of the first current switch transistor element, the output emitter follower transistor element and cross-control circuit emitter follower transistor element of each emitter follower transistor means being coupled together with a common base node coupling to the respective first or second output node of the ECL/CML circuit.

Claim 8

An improved emitter coupled logic or current mode logic (ECL/CML) circuit having active switching first and second output nodes respectively providing true and complementary output signals of high and low potential, output buffer first and second emitter follower transistor means operatively coupled respectively to the first and second output nodes for sourcing said output signals to respective true and complementary outputs, and output current sink means operatively coupled for sinking current respectively from the true output and first emitter follower transistor means and from the complementary output and second emitter follower transistor means, the improvement comprising: first current switch transistor element operatively coupled between the first emitter follower transistor means said output current sink means; first cross-control circuit coupled between the emitter node of the second emitter follower transistor means and the base node of the first current switch transistor element for controlling the conducting state of the first current switch transistor element so that it is on (conducting) and off (non-conducting) for complementary output signals of high and low potential respectively; second current switch transistor element operatively coupled between the second emitter follower transistor means and said output current sink means; and second cross-control circuit coupled between the emitter node of the first emitter follower transistor means and the base node of the second current switch transistor element for controlling the conducting state of the second current switch transistor element so that it is on (conducting) and off (non-conducting) for true output signals of high and low potential respectively; said first emitter follower transistor means comprising a true output emitter follower transistor element coupled to the true output and a second cross-control circuit emitter follower transistor element coupled to control the conducting state of the second current switch transistor element, and said second emitter follower transistor means comprising a complementary output emitter follower transistor element coupled to the complementary output and a first cross-control circuit emitter follower transistor element coupled to control the conducting state of the first current switch transistor element, the output emitter follower transistor element and cross-control circuit emitter follower transistor element of each emitter follower transistor means being coupled together with a common base node coupling to the respective first or second output node of the ECL/CML circuit.

Claim 9

The ECL/CML circuit of claim 6 wherein the first cross-control circuit comprises the first cross-control circuit emitter follower transistor element, a first resistor element, a first diode element, and control circuit current sink means coupled in series, the node between said first resistor element and first diode element being coupled to the second current switch transistor element and wherein the second cross-control circuit comprises said second cross-control circuit emitter follower transistor element, second resistor element, second diode element and control circuit current sink means coupled in series, the node between the second resistor element and second diode element being coupled to the first current switch transistor element.

Claim 10

The ECL/CML circuit of claim 7 wherein the sinking current generated by the output current sink means is substantially greater than the sinking current generated by the control circuit current sink means.

Claim 11

The ECL/CML circuit of claim 7 wherein the output current sink means comprises a single current sink coupled current switch transistor elements.