Patent US4943740A successfully refreshed from Google Patents.
US4943740A
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US
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Ultra fast logic
Assignee: Individual
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Filing: 1988-04-12
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Granted: 1990-07-24
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Expires: 2008-04-12
Abstract
Abstract The logic has an extremely high speed, very low number of components and large common mode rejection, and is intended to eliminate the emitter-coupled logic (ECL). The supply voltage and power consumption are small. The logic is particularly for digital systems requiring extremely fast and complex digital processing, such as supercomputers. One basic gate is responsive to and providing differential binary signals, and comprises a pair of transistors of opposite conductivity types, each having a base, emitter and collector, wherein the bases are separately coupled to gate inputs, the emitters are coupled together, and the collectors are separately coupled to gate outputs and further to a power supply via biasing resistors. Based on the basic gate is a memory cell which includes a positive feedback resistor and can be read and written via a single terminal.
Inventors
- 👤 Zdzislaw Gulczynski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:55
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/20; H03K19/21; H03K19/212; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
114 words
Logic apparatus providing differential binary output signal in response to differential binary input signal, comprising: a pair of input terminals with the differential binary input signal applied thereacross; a pair of output terminals with the differential binary output signal appearing thereacross; a pair of transistors of opposite conductivity types, each having a base, emitter and collector electrodes, wherein the base electrodes are separately coupled to the inputs, one emitter electrode provides a signal to the other emitter electrode in the absence of an input or output taken therefrom and the collector electrodes are separately coupled to the outputs; and a pair of means for biasing the transistors, separately coupled to the collector electrodes thereof.
Claim 2
Dependent Claim
114 words
Logic apparatus providing differential binary output signal in response to differential binary input signal, comprising: a pair of input terminals with the differential binary input signal applied thereacross; a pair of output terminals with the differential binary output signal appearing thereacross; a pair of transistors of opposite conductivity types, each having a base, emitter and collector electrodes, wherein the base electrodes are separately coupled to the inputs, one emitter electrode provides a signal to the other emitter electrode in the absence of an input or output taken therefrom and the collector electrodes are separately coupled to the outputs; and a pair of means for biasing the transistors, separately coupled to the collector electrodes thereof.
Claim 3
Dependent Claim
29 words
Apparatus of claim 1 further including one or two diode means each coupled between the base and collector electrodes of one of the transistors for preventing a saturation thereof.
Claim 4
Dependent Claim
22 words
Apparatus of claim 1 wherein at least one means for biasing includes a voltage source and a resistor coupled in series therewith.
Claim 5
Dependent Claim
15 words
Apparatus of claim 1 wherein at least one means for biasing includes a current source.
Claim 6
Dependent Claim
23 words
Apparatus of claim 1 further including an input means for applying the differential binary input signal to the base electrodes of the transistors.
Claim 7
Dependent Claim
19 words
Apparatus of claim 5 wherein the input means includes a resistor coupled between the base electrodes of the transistors.
Claim 8
Dependent Claim
17 words
Apparatus of claim 5 wherein the input means includes a resistor coupled in series with one input.
Claim 9
Dependent Claim
32 words
Apparatus of claim 5 further including one or two diode means each coupled between one of the inputs and the collector electrode of one of the transistors for preventing a saturation thereof.
Claim 10
Dependent Claim
33 words
Apparatus of claim 1 further including an input means having a third input terminal for providing the differential binary input signal in response to a single binary signal applied to the second input.
Claim 11
Dependent Claim
29 words
Apparatus of claim I further including an output means having a third output terminal, for providing a single binary signal thereat in response to the differential binary output signal.
Claim 12
Dependent Claim
21 words
Apparatus of claim 1 further including means for applying the signal of the one emitter electrode to the other emitter electrode.
Claim 13
Dependent Claim
12 words
Apparatus of claim 11 wherein the means for applying includes a resistor.
Claim 14
Dependent Claim
72 words
Apparatus of claim 11 wherein the means for applying includes: a pair of second inputs; and a pair of second transistors of opposite conductivity types, each having a base electrode separately coupled to one of the second inputs, an emitter electrode providing a second signal to the emitter electrode of the other second transistor, and a collector electrode coupled to the emitter electrode of the first said transistor of even conductivity type.
Claim 15
Dependent Claim
111 words
Bistable logic apparatus, comprising: a pair of inputs and an output; a pair of transistors of opposite conductivity types, each having a base, emitter and collector electrodes, wherein the base electrodes are separately coupled to the inputs, one emitter electrode provides a signal to the other emitter electrode in the absence of an input or output signal taken therefrom and the collector electrode of one transistor is coupled to the output; a pair of means for biasing the transistors separately coupled to the collector electrodes thereof; and a resistive means for applying a signal appearing at the collector electrode of the one transistor to the base electrode of the other transistor.
Claim 16
Dependent Claim
111 words
Bistable logic apparatus, comprising: a pair of inputs and an output; a pair of transistors of opposite conductivity types, each having a base, emitter and collector electrodes, wherein the base electrodes are separately coupled to the inputs, one emitter electrode provides a signal to the other emitter electrode in the absence of an input or output signal taken therefrom and the collector electrode of one transistor is coupled to the output; a pair of means for biasing the transistors separately coupled to the collector electrodes thereof; and a resistive means for applying a signal appearing at the collector electrode of the one transistor to the base electrode of the other transistor.
Claim 17
Dependent Claim
15 words
Apparatus of claim 14 wherein at least one of the transistors is of Schottky type.
Claim 18
Dependent Claim
22 words
Apparatus of claim 14 wherein at least one means for biasing includes a voltage source and a resistor coupled in series therewith.
Claim 19
Dependent Claim
24 words
Apparatus of claim 14 including one or two source means for providing predetermined signals, wherein the source means are separately coupled to the inputs.
Claim 20
Dependent Claim
32 words
Apparatus of claim 14 further including a second output coupled to the collector electrode of the other transistor, wherein a differential binary output signal appears between the first said and second outputs.
Claim 21
Dependent Claim
31 words
Apparatus of claim 14 further including a second resistive means for applying a signal appearing at the collector electrode of the other transistor to the base electrode of the one transistor.
Claim 22
Dependent Claim
23 words
Apparatus of claim 14 further including a resistive means for applying the signal of the one emitter electrode to the other emitter electrode.
Claim 23
Dependent Claim
14 words
Apparatus of claim 14 further including a switch coupled in series with the output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-23 | 1994-01-22 | 1994-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-23 | 1998-01-22 | 1998-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-23 | 2002-01-22 | 2002-07-24 | $7700.00 | Window Closed / Lapsed |